International Journal of Embedded Systems  (IJES)
ISSN (Online): 1741-1076  -  ISSN (Print): 1741-1068

Published in 4 issues per year  (View Subscription Price)

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Abstracting/Indexing Services and Journal Lists

   Objectives

The objective of IJES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on embedded systems.

   Readership

Scientists, engineers, researchers, graduate students, educators, managers and industrial professionals.

   Contents

IJES is a refereed international journal, initially published in 6 issues per year, providing an international forum to report, discuss and exchange experimental or theoretical results, novel designs, work-in-progress, experience, case studies, and trend-setting ideas. Papers should be of a quality that represents the latest advances in embedded systems in time-to-market, cost, code size, weight, testability, power, real-time behaviour, and stimulating future trends.

   Subject Coverage

IJES covers all aspects of the embedded computing systems. Topics of interest include, but are not limited to:

Embedded System Architecture:

• Heterogeneous multiprocessors, reconfigurable platforms, memory management support, communication, protocols, network-on-chip, real-time systems, and embedded microcontrollers, etc.

Embedded Software:

• Compilers, assemblers and cross-assemblers, programming, memory management, object-oriented aspects, virtual machines, scheduling, concurrent software for SoCs, distributed/resource aware OS, OS and middleware support, etc.

Embedded Hardware:

• System-on-a-chip, DSPs, hardware specification, synthesis, modelling, simulation and analysis at all levels for low power, power-aware, testable, reliable, verifiable systems, performance modelling, validation, security issues, real-time behaviour, and safety critical systems, etc.

Application-specific Processors and Devices:

• Network processors, real-time processor, media and signal processors, application-specific hardware accelerators, reconfigurable processors, low power embedded processors, bio/fluidic processors, bluetooth, handheld devices, flash memory chips, etc.

Real-time Systems:

• All real-time related aspects such as software, parallel and distributed real-time systems, real-time kernels, real-time OS, task scheduling, multitasking design, etc.

Hardware/Software Co-design:

• Methodologies, test and debug strategies, real-time systems, interaction between architecture and software design, specification and modelling, design representation, synthesis, partitioning, estimation, design space exploration beyond traditional hardware/software boundary, theory and algorithms, etc.

Testing Techniques:

• All aspects of testing, including design-for-test, test synthesis, built-in self-test, and embedded test, for embedded and system-on-a-chip systems.

Industrial Practices and Benchmark Suites:

• System design, processor design, software, tools, case studies, trends, emerging technologies, experience maintaining benchmark suites, representation, interchange format, copyrights, maintenance, reference implementations, and metrics, etc.

Embedded System Education:

• Courses, textbooks, teaching tools and methods.

Emerging New Topics:

• New challenges for next generation embedded computing systems, arising from new technologies (e.g., nanotechnology), new applications (e.g., pervasive or ubiquitous computing, embedded internet tools), new principle (e.g., embedded engineering), etc.

   Specific Notes for Authors

Submitted papers should not have been previously published nor be currently under consideration for publication elsewhere. (N.B. Conference papers may only be submitted if the paper was not originally copyrighted and if it has been completely re-written).

All papers are refereed through a double blind process. Authors will be required to prepare their final manuscripts using either LaTex or Word in Inderscience's A4 size (double column) journal style. For LaTex, figures must be prepared in PostScript and appropriately incorporated into the text. A guide for authors, sample copies and other relevant information (including LaTex and Word templates) for submitting papers are available on the Submission of Papers web-page.

You may send one copy of the manuscript in the form of a PostScript or PDF file, with the final, complete files in a TAR or ZIP folder containing all sources (LaTex, figures and bibliography) together, attached to an e-mail (details of file formats in Author Guidelines) to Prof. Laurence T. Yang or Prof. Minyi Guo

Please include in your submission the title of the Journal

   Editors and Members of the Editorial Board

Editor(s) in Chief

Prof. Minyi Guo
Shanghai Jiao Tong University
Department of Computer Science and Engineering
Shanghai 200240
P.R. CHINA
guo-my@cs.sjtu.edu.cn
 
Prof. Laurence T. Yang
St. Francis Xavier University
Department of Computer Science
Antigonish, NS, B2G 2W5
CANADA
ltyang@gmail.com

Advisory Board

Prof. K.H. (Kane) Kim
University of California at Irvine
USA

Editorial Board Members

Prof. Tarek F. AbdelzaherTa
University of Virginia
USA

Prof. Hamid R. ArabniaHa
University of Georgia
USA

Dr. Felice BalarinFe
Cadence Berkeley Labs
USA

Prof. Sanjoy K. BaruahSa
University of North Carolina at Chapel Hill
USA

Prof. Azer BestavrosAz
Boston University
USA

Prof. Shuvra S. BhattacharyyaSh
University of Maryland
USA

Prof. Azzedine BoukercheAz
University of Ottawa
USA

Prof. Vipin ChaudharyVi
Wayne State University
USA

Prof. Albert M. K. ChengAl
University of Houston
USA

Prof. Alexander G. DeanAl
North Carolina State University
USA

Prof. Ed DeprettereEd
Leiden University
NETHERLANDS

Prof. Nikil DuttNi
University of California at Irvine
USA

Prof. Stephen A. EdwardsSt
Columbia University
USA

Prof. Michael González HarbourMi
Universidad de Cantabria
SPAIN

Prof. Reiner HartensteinRe
Kaiserslautern University of Technology
GERMANY

Prof. Susumu HoriguchiSu
Tohoku University
JAPAN

Prof. Harry C. HsiehHa
University of California at Riverside
USA

Prof. Pao-Ann HsiungPa
National Chung Cheng University
TAIWAN, ROC

Prof. Xiaobo Sharon HuXi
University of Notre Dame
USA

Prof. Young-Sik JeongYo
Wonkwang University
KOREA, REPUBLIC OF

Prof. Lizy Kurian JohnLi
University of Texas at Austin
USA

Prof. Dr. Jörg KaiserJö
University of Ulm
GERMANY

Prof. Andreas KrallAn
Technische Universität Wien
AUSTRIA

Prof. Ulrich KremerUl
Rutgers University
USA

Prof. Christian LandraultCh
LIRMM
FRANCE

Prof. Hsien-Hsin (Sean) LeeHs
Georgia Institute of Technology
USA

Dr. Shih-Wei LiaoSh
Microprocessor Technology Labs, Intel
USA

Prof. Bill LinBi
University of California
USA

Prof. Man LinMa
St. Francis Xavier University
CANADA

Prof. Lucia Lo BelloLu
University of Catania
ITALY

Prof. Govindarasu ManimaranGo
Iowa State University
USA

Prof. Rami MelhemRa
University of Pittsburgh
USA

Prof. Krishna PalemKr
Georgia Institute of Technology
USA

Prof. Viktor K. PrasannaVi
University of Southern California
USA

Prof. Franz-Josef RammigFr
University of Paderborn
GERMANY

Prof. Martin RemMa
Eindhoven University of Technology
NETHERLANDS

Prof. Masaaki ShimasakiMa
Kyoto University
JAPAN

Prof. Per StenstromPe
Chalmers University of Technology
SWEDEN

Prof. Janos SztipanovitsJa
Vanderbilt University
USA

Prof. Hiroaki TakadaHi
Nagoya University
JAPAN

Prof. Hiroyuki TomiyamaHi
Nagoya University
JAPAN

Prof. Martin TorngrenMa
Royal Institute of Technology (KTH)
SWEDEN

Prof. Tullio VardanegaTu
Università di Padova
ITALY

Prof. Zhaohui WuZh
Zhejiang University
P.R. CHINA

Prof. Hans-Joachim WunderlichHa
University of Stuttgart
GERMANY

Prof. Li XieLi
Nanjing University
P.R. CHINA

Prof. Jingling XueJi
University of New South Wales
AUSTRALIA

Prof. Toshitsugu YubaTo
University of Electro-Communication
JAPAN

Prof. Nakamura YukihiroNa
Kyoto University
JAPAN