International Journal of Embedded Systems (8 papers in press)

Regular Issues

• Energy-efficient fixed priority scheduling for imprecise mixed-criticality tasks on multi-processor platforms  
  by Yi-Wen Zhang, Chen Ouyang, Rong-Kun Chen 
  Abstract: The multiprocessor platform has become the mainstream in embedded systems, and energy consumption has become a challenge for these systems. In this paper, we consider the energy-efficient fixed priority partitioned scheduling problem of the imprecise mixed-criticality (IMC) tasks on a multiprocessor platform. We propose a novel IMC task partitioning algorithm (IMCSGA) to minimize energy consumption under the Criticality Rate Monotonic Scheduling. The experimental results show that IMCSGA can save about 8.48% energy consumption compared with the existing methods.
  Keywords: energy-aware; imprecise mixed-criticality; fixed priority; partitioned scheduling; genetic algorithm.
  DOI: 10.1504/IJES.2025.10077359
   
  
• An IoT-integrated energy-efficient monitoring and preservation system for perishable crops  
  by Md. Iftekharul Mobin, Mahamodul Hasan Mahadi, A.F.M. Suaib Akhter, Al-Sakib Khan Pathan 
  Abstract: This paper presents an IoT-enabled post-harvest monitoring and decision support system for perishable crops, such as onions, using real-time environmental sensing and a Bayesian network model to forecast spoilage. The system integrates multiple sensors to continuously monitor storage conditions and crop health. The data collected are fed into the Bayesian network, enabling probabilistic reasoning about spoilage risk and profitability. In parallel, machine learning models linear regression (LR), support vector regression, and artificial neural networks were trained to predict weight loss, with LR achieving the lowest mean absolute error (1.61). The system demonstrated a 94% probability of preventing rot and a 79% probability of ensuring profitability under optimised conditions. Furthermore, intelligent alarms and blower control based on real-time sensor input significantly reduced both rot risk and energy consumption. The framework can be adapted to various perishable agricultural commodities.
  Keywords: digital agriculture; energy efficient; IoT-integrated; post-harvest optimisation; storage efficiency.
  DOI: 10.1504/IJES.2026.10076605
   
  
• MILP-based difference probabilities of PRESENT and Keccak  
  by Guoyong Han, Hongluan Zhao, Yang Gao, Wanxuan Yan, Yixuan Wu, Jinxin Wu 
  Abstract: Mixed integer linear programming (MILP) model is one of the best tools to search differential trails for bit-oriented block ciphers. Based on this method, it is easy to evaluate block ciphers against differential attack. This paper focuses on the research to search for better distinguishers of block cipher PRESENT-80 and Keccak-f[400]. The 14/15/16-round differential distinguisher of PRESENT-80 with the probability of no less than 2^-71/2^-75/2^-79 is obtained. A 17-round differential path (the start with two active S-boxes) with no less than 2^-76 is shown. For Keccak-f[400], the 3/4/5-round differential characteristics with the probabilities of 2^-156/2^-284/2^-385 are presented. Better differential cryptanalysis results can be obtained based on the above superior distinguishers. This paper provides a reference to find better and more accurate differential paths to attack block ciphers, and presents a detailed calculation process of them. The limitation of this paper lies in the fact that the current distinguishers have not been used for specific cryptanalysis.
  Keywords: mixed integer linear programming; MILP; differential probabilities; PRESENT-80; Keccak-f[400].
  DOI: 10.1504/IJES.2025.10074128
   
  
• Porting sequential haze removal using dark channel prior to hybrid OpenMP and CUDA  
  by Ling-Huey Li, Tien-Hsiung Weng, Meng-Yen Hsieh, Hung-Lung Tsai, Arcangelo Castiglione 
  Abstract: Image dehazing has been used in many applications, such as underwater imaging, autonomous, aerial, and drone vehicles, as well as surveillance and security. While it is common today to use combinations of CPUs and GPUs in heterogeneous computing environments, we present in this work the development of a parallel hybrid approach using CUDA and OpenMP to enhance the efficiency of the dark channel prior algorithm for haze removal. Implementation techniques and result discussions regarding program improvements may be used to support parallel developers. Preliminary studies, results, and experiments on hybrid CUDA and OpenMP have shown promising outcomes.
  Keywords: image dehaze; haze removal; dark channel prior algorithm; OpenMP; CUDA.
  DOI: 10.1504/IJES.2025.10074135
   
  
• Efficient DMA and shuffling co-processing method of half-word data blocks for vector digital signal processor  
  by Jingcheng Xiong, Yonghua Hu, Xin Zhang, Zeming Liao 
  Abstract: Though vector digital signal processors (DSPs) have abundant hardware resources for data processing, word alignment is typically required by their vector memory access and data transmission components. However, in some DSP applications which process half-word data blocks, word alignment requirement may be not satisfied because there is an interval also in half-word between adjacent valid data elements. Thus, for the highly effective processing of half-word data blocks in a vectorised way under the word alignment requirement, this paper proposes a DMA and half-word vector shuffling (DHWVS) co-processing method. The DHWVS co-processing method is classified according to the adjacent data stride and the alignment characteristic of data block address. Besides, the DMA function and vector shuffle function of vector DSP are used to reduce the demand of memory accessing. The experiment results show that the performance of the algorithms optimised by our method is significantly improved, and the maximum speedup ratio reaches 16.1.
  Keywords: vector DSP; half-word data; indexed DMA; vector shuffling; parallel data processing.
  DOI: 10.1504/IJES.2026.10077351
   
  
• Linearising compiling method of loops handling specified data amounts in VLIW architectures  
  by Xinlian Zhou, Peng Liu, Yonghua Hu, Aobo Cheng, Zhuoyou Tang, Wei Liang 
  Abstract: Longer basic blocks can provide greater opportunity for the instruction-level parallelism of loops on very long instruction word (VLIW) architectures. This paper proposes a compilation method of loop linearisation (LLU) for loops with fixed iteration number. The method can eliminate the loop structure from corresponding input loops by rearranging the instructions of loop iterations, and it removes all the instructions for loop control. These make the subsequent instruction scheduling more effective. This paper investigates the problems of auto analysing the number of loop iterations and the corresponding code generation method, and proposes the algorithms to solve them. Experimental research is conducted on the FT-M7002 hardware platform. The results show that compared to loop unrolling, the proposed method achieves a minimum average performance improvement of 7% and a maximum improvement of 28%. For data-intensive computing circumstances, this method can be used to accelerate the response speed of related applications.
  Keywords: loop unrolling; LLU; compilation optimisation; very long instruction word; VLIW.
  DOI: 10.1504/IJES.2026.10077350
   
  
• Optimising Java bytecode execution performance on embedded systems using instruction set enhancement  
  by Adeel Iqbal, Minhaj Ahmad Khan 
  Abstract: Optimising the execution of Java bytecode on embedded systems is essential for various applications, considering the limitations of their resources, such as storage and processing power. In this regard, using the conventional profilers available to analyse bytecode, identifying basic blocks, determining frequencies, and defining new superinstructions for every basic block is cumbersome and time-consuming. This paper presents a novel approach to enhance the performance of embedded systems through the integration of superinstructions into Java bytecode. The proposed approach performs bytecode analysis, identifies basic blocks along with the specific candidate instructions suitable as superinstructions through an efficient profiler, and subsequently replaces these instructions with optimised superinstructions. The instruction set enhancement and reduced stack operations result in better execution performance of the applications running on embedded systems. The approach implemented in our prototype framework, JEOPT, has been used to optimise the execution of complex mathematical benchmarks including matrix multiplication and LU factorisation. The experimental results demonstrate that our proposed approach significantly improves the execution time of matrix multiplication and LU factorisation up to 4.65% and 2.12%, respectively.
  Keywords: dynamic program analysis; embedded software; embedded systems; interpreter; Java; Java bytecode optimisation; performance optimisation; superinstructions.
  DOI: 10.1504/IJES.2025.10075611
   
  
• A study on intelligent in-class education quality assessment pattern bottom on improved support vector machine  
  by Yang Li, Haiyu Zhang 
  Abstract: In response to the problem that existing teaching quality assessment techniques cannot comprehensively evaluate teaching quality from multiple dimensions, this study uses class distance and approximate complete binary tree generation strategies to reduce the variance of sample data, and establishes an intelligent classroom teaching quality evaluation model based on distance binary tree support vector machine. The results showed that the classification accuracy of the proposed algorithm on three datasets was 97.32%, 98.5%, and 97.46%, respectively, and the training time was 23.2 ms, 23.7 ms, and 23.8 ms. The accuracy of the proposed algorithm was 0.71, and the area under curve was 0.92. When the data reached 400, the training and testing time of the proposed algorithm was 16.3 ms and 4.0 ms, respectively. The research results contribute to improving the scientific and reliable evaluation of teaching quality, thereby helping teaching managers better understand teaching effectiveness and improve teaching quality.
  Keywords: Euclidean distance; support vector machine; binary tree; intelligent classroom; teaching quality; evaluation pattern.
  DOI: 10.1504/IJES.2026.10077352