International Journal of High Performance Systems Architecture
2016 Vol.6 No.1
Special Section Editorial |
Pages | Title and author(s) |
1-12 | On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS toolMageda Sharafeddin; Mazen A.R. Saghir; Haitham Akkary; Hassan Artail; Hazem Hajj DOI: 10.1504/IJHPSA.2016.076197 |
13-27 | KUMMS: optimising DRAM locality with Kernel-user behavioursBeilei Sun; Xi Li; Chao Wang; Bo Wan; Xuehai Zhou DOI: 10.1504/IJHPSA.2016.076202 |
Special Section on Innovative Design Method for Smart Concurrent Systems | |
28-35 | Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs Burhan Khurshid; Roohie Naaz DOI: 10.1504/IJHPSA.2016.076205 |
36-50 | Slider: an online and active deadlock avoider by serial execution of critical sectionsZhen Yu; Xiaohong Su; Peijun Ma DOI: 10.1504/IJHPSA.2016.076193 |
51-60 | Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagramsJ.P. Anita; P. Sudheesh DOI: 10.1504/IJHPSA.2016.076204 |