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International Journal of High Performance Systems Architecture

International Journal of High Performance Systems Architecture (IJHPSA)

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International Journal of High Performance Systems Architecture (17 papers in press)

Regular Issues

  • A Distributed Big Data Analytics Model for People Re-identification Based Dimensionality Reduction   Order a copy of this article
    by Abderrahmane Ez-zahout 
    Abstract: Big data analytics is a vast domain includes intelligent processing systems. Video intelligent surveillance is one of them which have been widely studied, because it generate a huge volume of data, various types of structured and unstructured data and all accompanied treatments require fast processing speed. In recent research areas like Big Data analytics, most of the data involved in the processing comes from video surveillance systems (CCTV systems) are unstructured. In real time CCTV systems, a very big volume of data requires an efficient and secure ingestion, storage and advanced processing. In the process of treatment, all this systems, operate on four phases, detection, tracking, profile analysis and re-identification using various approaches. Intelligent person re-identification process using only the visual information is challenging for several reasons. In the current work, An efficient re-identification algorithm based on SparkMlLib Core is adopted. The Minkowski distance and kmeans algorithms geted from SparkMlLib are used to speed up the features similarity searching. CMC and CDF curves, have functionally explains the importance of this contribution. This function measures the re-identification errors. Then, a principal component analysis is used to reduce the similarity database.
    Keywords: (SparkMlLib; CCTV Systems; Re-identification; ROI; Features Similarity; CMC; CDF; PCA).

  • A CAD Approach For Power Supply Noise Aware Floorplan In SoC   Order a copy of this article
    by PARTHA MITRA, Jaydeb Bhaumik, Angsuman Sarkar 
    Abstract: This paper deals for reduction of power supply noise with decoupling capacitor estimation and allocation using particle swarm optimization algorithm at the floorplanning stage of the physical design process. Decoupling capacitors are allocated between the power and ground rails in parallel with functional blocks having supply noise effectively reduces rapid fluctuations in supply voltage. Decoupling capacitors placed far away does not have much effect on the power supply noise and hence placement of decoupling capacitors is also a major focus in this work. Excess capacitors increases the delay and power parameters and degrades the overall performance of the integrated circuit. In this work the major focus is on optimizing the decoupling capacitor budget and placement of decoupling capacitors so that the voltage noise margin can be reduced significantly and also the various design parameters remain unaltered as much as possible. In this work peak supply noise has been reduced by up to 69.5%, increment in delay and power parameters is 6.52% and 2.08% with decoupling capacitor allocation. Maximum increment in core area is 6.57% with decoupling capacitor allocation. The decoupling capacitor budget has also been optimized by up to 36.7%. This CAD approach can be used power supply noise reduction for any multi-core architecture.
    Keywords: Computer Aided Design(CAD); Decoupling Capacitor(decap); Particle Swarm Optimization(PSO); Power Distribution Network(PDN); System-on-Chip(SoC); White Space(WS).

  • ACS: An Alternate Coding Scheme to Improve Degrade Read Performance for SSD-based RAID5 Systems   Order a copy of this article
    by Yubiao Pan, Mingwei Lin 
    Abstract: To guarantee high performance and reliability, storage systems require better devices and data redundancy schemes, e.g., SSD-based RAID5. However, failures in the large-scale storage systems are common. In order to serve requests on a failed node, the SSD-based RAID5 causes additional disk I/Os to trigger degraded reads, thus suffering performance degradation. Existing coding methods are not suitable for the SSD-based RAID5. How to maintain the same storage cost as the traditional RAID5 does while obtaining less disk I/Os for degraded reads is an interesting problem. To address this problem via coding aspect, we first come up with an Alternate Coding Scheme (ACS) by using the characteristics of SSD to reduce disk I/Os for boosting degraded reads. To work for realistic workloads, we further propose ACS-W and ACS-DR approaches for write and degraded requests. Our evaluations based on the trace-driven simulator with real-world workloads show that compared to the traditional method, ACS indeed reduces disk I/Os and improves the degraded read performance.
    Keywords: Solid-state Drives; RAID; Degrade Read; Disk I/Os; Performance.

  • Efficient hardware implementation of TEA, XTEA and XXTEA ciphers for low resource IoT applications   Order a copy of this article
    by Zeesha Mishra, Bibhudendra Acharya 
    Abstract: The advancement in network connectivity and data handling capabilitiesrnshows the tremendous growth of Internet of Things (IoT). The number of connected devices in IoT applications has been increasing, leaving serious security concerns. The problem of providing security solutions to resource-constrained devices leads to lightweight cryptographic algorithms. Among instances when the data security in resource constrained environment i.e. smart devices are to be taken into consideration, lightweight encryption algorithms admit in popularity and are deemed to be of great merit. Reduction of both power consumption and area are always a major concern. Tiny Encryption Algorithm (TEA) is one of the lightweight cryptographic algorithm with block size of 64-bit and key size of 128-bit follows Feistel network structure and further this algorithm is modified as Extended Tiny Encryption Algorithm (XTEA) and Corrected tiny encryption algorithm (XXTEA). This paper have proposed highly efficient roundbased architectures of TEA, XTEA and XXTEA to make them suitable for the low area, low power applications. The strategy is to optimize the hardware design for low resource applications. All the three proposed architectures are extensively evaluated and compared on the basis of performance, and area utilization for their implementations in different FPGA platforms.
    Keywords: IoT; lightweight cryptography; TEA algorithm; XTEA algorithm; Fiestelrnstructure; FPGA; throughput; slices.

  • Effective hardware architectures for LED and PRESENT ciphers for resource-constrained applications   Order a copy of this article
    by Piyush Modi, Pulkit Singh, Bibhudendra Acharya 
    Abstract: Existing cyber physical systems (CPS) and IoT services depend largely on the widespread implementation of tiny smart devices for tracking, storing, monitoring, and networking applications. All IoT-enabled devices, including consumer smart devices, need secure communication mechanisms. In this paper, three different architectures are proposed based on LED and PRESENT lightweight block ciphers targeting at resource-constrained applications. This article discusses two specific hardware architectures for the LED cipher. The first architecture introduces a round-based pipelined design in which pipeline registers are inserted in between round operations. Whereas the second is a serialized architecture that runs on a single cell per clock cycle. These proposed designs offer very efficient area-throughput trade-off. In addition, we proposed a 32-bits datapath optimization design to achieve high-performance, low-power, and energy-efficient hardware of PRESENT cipher encryption system. Various FPGA platforms are used for hardware implementation and results are evaluated and compared with other related works.
    Keywords: Internet-of-Things (IoT); PRESENT; LED; Block cipher; Cyber Physical System (CPS); Field Programmable Gate Array (FPGA); etc.

  • Multithreading on reconfigurable hardware: A performance evaluation approach of a multicore FPGA architecture   Order a copy of this article
    by George K. Adam 
    Abstract: This paper addresses the performance issues of multiple threads running on a multithreaded FPGA multicore architecture, supported by a real-time variant of Linux operating system. The objective is to investigate the efficiency of running in parallel and concurrently multithreaded applications and evaluate performance metrics including execution time, speedup, response latency, and CPU and memory usage. The development platform is a 16-core architecture implemented with Nios II soft processors on an ALTERA Cyclone IV FPGA. Performance is analyzed and evaluated based upon the development and implementation of an iterative algorithm for the generation and execution of multithreaded tasks. Experimental tests were executed in a number of cores configurations and threads combinations under different workloads, such as matrix multiplication and read-write operations on on-chip memory. The results confirm the validity of the proposed approach in running and evaluating efficiently multithreaded tasks in real-time with noticeable performance improvements in terms of timing features.
    Keywords: FPGA; field programmable gate arrays; real-time operating systems; multicore; multithreading; performance measurement.

Special Issue on: Advances in Multi-Core and Many-Core Systems

  • Knowledge-based mining with the game-theoretic rough set approach to handling inconsistent healthcare data   Order a copy of this article
    by Abhay Kumar Singh, Muhammad Rukunuddin Ghalib 
    Abstract: Healthcare data analysis played a crucial role in the medical industries for examining the medical data. Primarily, in smart healthcare applications, a massive volume of data must be handled and processed to make clinical decisions. This clinical analysis process requires more time and complexity due to the high-dimensionality data. Therefore, machine learning and intelligent techniques are introduced in the healthcare data analysis field to improve data processing. This paper focuses on developing knowledge-based mining with a game-theoretic rough set (KM-GTRS) based healthcare data analysis process. The knowledge mining process able to handling the high-dimensional data and providing the data to the application-centric services. Here the introduced game-theoretic rough set algorithm analyzing the medical data and capable of handling the decision regarding the inconsistent and missing data effectively. In addition to this, the method ensures the solutions for medical data analysis with minimum time. The sufficient identification of inconsistent data improves the overall medical analysis recognition accuracy. This process achieves the minimum analysis time, computation complexity, inconsistency, and service latency.
    Keywords: Big Data; Healthcare; Knowledge Base; Linear Programming; Machine Learning.

  • Evaluation of Flexural and Shear Property of High Performance PLA/Bz Composite Filament Printed at Different FDM Parametric Conditions   Order a copy of this article
    by Sneha P, Balamurugan K, Kalusuraman G 
    Abstract: The reinforcement of metal in the Polylactic acid (PLA) matrix provides significant changes in improving the material properties, particularly for 3D-printing. In the present work, 14% of Bronze (Bz) that has the particle size of 10-20
    Keywords: PLA-Bz; Fused deposition model; Density; Bend; Shear; Optical microscopy.

  • Pervasive Hybrid Two-Stage Fusion Model of Intelligent Wireless Network Security Threat Perception   Order a copy of this article
    by Feilu Hang, Linjiang Xie, Wei Guo, Yao Lv, Wei Ou, A. Shanthini 
    Abstract: The rapid development of software, hardware, and communications technologies has helped spread sensors, actuators, and heterogeneous devices connected through the internet, collecting and distributing a large amount of information, opening a unique class of advanced services available at any time. This paper introduced a Pervasive Hybrid two-stage fusion model (PHTSFM) for the cybersecurity situation evaluation and focused on multi-heterogeneous sensors to determine the impact of security threats on a networked system and precisely evaluate system safety. The multisource information\'s characteristics in network security analysis and data fusion security algorithms have been introduced. Multiple correlations are utilized to differentiate the normal event or outlier and abnormal event within the least delay. The simulated network assessment reveals that the proposed solution is appropriate for the network environment, and the findings of the test are precise and effective.
    Keywords: Fusion Model; Intelligent Network Security; Threat Detection; Hybrid Two-stage Model Fusion Model.

  • Multimodal Information Interaction and Fusion for The Parallel Computing System Using AI Techniques   Order a copy of this article
    by Yang Li, Wei Li, Na Li, Xiaoli Qiu, Parthasarathy Poovendran, KARTHIK BALA MANOKARAN 
    Abstract: Recently multimodal information fusion systems are popularly used to increase the reliability of recognition systems. These systems employ data from different modalities. Since different modalities capture information with different attributes, the fusion of this information aids in achieving better solutions. In this research, we present a Multimodal Fusion for Parallel Computing scheme. Here, a novel Multi-modal Fusion-based Parallel Computing (MMFPC) Model is being proposed. Besides, a new technique for the generation of history images is also proposed. Feature extraction using GLCM and HOG features is performed. The fusion of multimodal features using the weighted fusion technique is proposed to prioritize the modes that contain more valuable data. Classification is analyzed using different artificial intelligence algorithms. Finally, the proposed scheme is evaluated using a public fall detection dataset. It was observed that the proposed system achieves a high accuracy of 96.77% and also a high specificity of 93.52%.
    Keywords: Multi-modal; parallel computing; artificial intelligence; fall.

  • Optimized embedded sensor network using multicore architecture for low power application   Order a copy of this article
    by Peng Li, Bo Mei, Yiran Wang 
    Abstract: Embedded infrastructure takes on a significant role in energy and efficiency since the Rise of the Internet of Things (IoT). Besides, energy management accomplishments linger on the darker side of science with the condition of elevated multicore embedded systems. Numerous algorithms were offered in embedded frameworks for productive use of switching frequency, including dynamically scaled rates, thread representation and scarcity methods. This system was used as energy efficiency modes for controlling power usage in the embedded interfaces. These approaches have, however, some bottlenecks that enable use in the embedded frameworks. In light of these, this study proposes a novel MCA-LPA technique that includes a robust learning device optimization for switching frequency by entry and core allotment based on the working load.rnThe suggested multicore architecture for low power application MCA-LPA model architecture consists of various steps in developing, classification and automating workloads using BAT equations and intense, profound learning predictions.
    Keywords: multicore architecture; power consumption; embedded sensor network; Optimization.

  • Reconfigurable architecture for Heterogeneous multi-Core and many-Core architecture with IoT assistance   Order a copy of this article
    by Xuefeng Xing, Jing Cao, Hongtao Zhou, Lei Song, Yanan Qiu 
    Abstract: This article discusses a multi-Core real-time device that is reconfigurable and has a sequence of configurations, each lifted to a predetermined state, executing different functions performed by the process. A complex system program is generated when implemented as processes. This situation is due to the increasing amount of threads and the consistency that can contribute to a growing energy usage between the individual installations. In this article, the Reconfigurable architecture for Heterogeneous multi-Core architecture (RA-HMCA) framework is proposed. However, researchers intend to simplify the program by preventing redundancies from being introduced and decrease the risk of threads when satisfying all necessary real-time requirements. The suggested solution employs multi-integer linear programming (MILP) technology in the scan stage to have a viable task model. An optically reconfigurable POSIX-based program creates a procedural performance of this technology. A research paper implementation and successful assessment support and validates the findings predicted.
    Keywords: multi-Core architecture; Reconfigurable architecture; Heterogeneous system; many-Core architecture; Internet of Things.

  • Network Security Defense System based on Artificial Intelligence and Big Data Technology   Order a copy of this article
    by Linjiang Xie, Feilu Hang, Wei Guo, Yao Lv, Wei Ou, FHA. Shibly 
    Abstract: Communication Network security is a defense against hacking, violence, and unwanted system modifications to access files and folders within a computer network. The increasing overlap between the physical and virtual realms of improved communication poses a problem of cybersecurity. To predict, identify, define, and resolve security risks, cybersecurity researchers depend on large quantities of security incidents. Hence, in this research, the Big Data Analytics based security system (BDASS) has been proposed to improve the communication network\'s security defense system with artificial intelligence. The big data sets representing multiple categories of data are used in big data analysis methods. Artificial intelligence offers algorithms that can think or learn and strengthen their behavior. A variety of automated systems currently are built on syntactic rules that are not necessarily sufficiently sophisticated to handle the degree of difficulty in the communication network system. The BDASS model achieves a less computation time ratio of 21.3%, misbehavior detection ratio of 97.5%, attack prediction accuracy ratio of 95.6%, possibility ratio of 96.4%, and success rate of 98.7% compared to other methods.
    Keywords: Artificial intelligence; Big Data Analytics; Communication Network security.

Special Issue on: EDIS2020 New Trends in Embedded and Distributed Systems Architecture and Applications

  • QASIS: A QoC aware Stress Identification System using Machine Learning Approach   Order a copy of this article
    by Souad Elhannani, Sidi Mohamed BENSLIMANE, KHALFI Mohammed Fethi, Mustafa Fechfouch 
    Abstract: Stress is a serious health problem that affects a large part of humanity. Early stress detection can help to prevent stress-related health problems. The Internet of Things (IoT) plays an important role in real time monitoring in the smart healthcare system. In this paper, we present an automatic stress detection system, called QASIS, to increases the effectiveness and efficiency of healthcare system to provide services. QASIS benefits of emerging wearable physiological sensors, specifically, electromyograph (EMG), electrocardiogram (ECG), and nasal/oral airflow, to monitors physical, cognitive and emotional stress. Our system uses an Extra Trees Classifier to achieve expected results in the areas such as car driving. We also illustrate how the reliability of the contextual information represented by QoC metrics, can enhance the accuracy of the stress detection system. We conducted a stress detection experiment with twenty-six subjects, and we confirmed that the proposed system could effectively detect stress, based on the measured breathing rate and the electrical activity of the heart and the muscles.
    Keywords: Internet of Things ; Quality of context (QoC); Healthcare system; Situation Identification; Stress detection; Machine learning; Extra Trees Classifier.

  • Optimization of Multi-objective Problems using An efficient Levy Flight Grasshopper Algorithm   Order a copy of this article
    by Dallel NASRI, Diab MOKEDDEM 
    Abstract: This paper is concerned in improving the performance of the nature-inspired multi-objective grasshopper optimization algorithm (MOGOA). The Levy flight technique is used for the first time to boost MOGOA algorithm by providing better solutions diversity. The proposed Levy flight trajectory-based multi-objective grasshopper optimization algorithm (LMOGOA) benefits from fast convergence speed to the true Pareto-optimal front and thus it overcomes MOGOA drawbacks of premature convergence and local optima stagnation. Then, LMOGOA algorithm is tested on a set of standard multi-objective problems(MOPs) and results proved significantly its outperformance compared to MOGOA algorithm.
    Keywords: multi-objective; grasshopper optimization algorithm; Levy flight trajectory; Constrained optimization.

  • A novel cooperative clustering approach based on multi-criteria decision-making for IoV   Order a copy of this article
    by Mahmoud Bersali, Abderrezak Rachedi, Hafida Bouarfa, Mohamed El Amine Badjara 
    Abstract: The introduction of the Internet of Things has gradually transformed conventional vehicular ad-hoc networks (VANETs) into a new paradigm known as the Internet of Vehicles (IoV), which has lately been the focus of several researchers. Frequent topological changes and the scalability issue are major problems that affect the performance of IoV. In order to overcome the previous challenges, we propose in this paper a novel cooperative clustering approach based on multi-criteria decision-making (MCDM) methods for IoV named: CMC-IoV, which combines both AHP and PROMETHEE methods to select the most appropriate leader for each cluster. CMC-IoV supports the cluster stability by selecting a Vice Cluster Leader as a complement to the Cluster Leader. We validate the efficiency of the proposed approach by using a realistic scenario from Highway 640 in Knoxville, USA as an input to the NS-3 network simulator.
    Keywords: VANET; Internet of Vehicles (IoV); MCDM; AHP; PROMETHEE; Clustering.

  • Memory-Processor co-scheduling for Real-time Tasks on Network-on-chip manycore architectures   Order a copy of this article
    by Chawki Benchehida, Mohammed Kamel Benhaoua, Houssam Eddine Zahaf, Giuseppe Lipari 
    Abstract: The Network-on-Chip (NoC) provides a viable solution to bus-contention problems in classical Multi/Many core architectures. However, NoC complex design requires a particular attention to support the execution of real-time workloads. It is necessary to take into account task-to-core allocation and inter-task communication, so that all timing constraints are respected. The problem is more complex when considering task-to-main-memory communication, as the main memory is off-chip and usually connected to the network edges, within the 2D-Mesh topology.rnrnIn this paper, we tackle these problems by considering the allocation of tasks and inter-task-communications, and memory-to-task communications (modeled using Directed Acyclic Graphs DAGs) at the same time, rather than separating them, as it has been addressed in the literature of real-time systems. This problem is highly combinatorial, therefore our approach transforms it at each step, to a simpler problem until reaching the classical single-core schedulability problem. The goal is to find a trade-off between the problem combinatorial explosion and the loss of generality when simplifying the problem. We study the effectiveness of the proposed approaches using a large set of synthetic experiments.
    Keywords: Real-time Systems; Network-on-Chip; SDRAM; Partitioned Scheduling; Task Allocation.