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International Journal of High Performance Systems Architecture

International Journal of High Performance Systems Architecture (IJHPSA)

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International Journal of High Performance Systems Architecture (6 papers in press)

Regular Issues

  • Heterogeneous Computing on Mobile GPU-FPGA Cooperation Platform   Order a copy of this article
    by Nan Hu, Xuehai Zhou, Xi Li 
    Abstract: In recent years, mobile GPUs have been widely adopted in Systems-On-Chip(SoCs) platforms, especially in the graphics area. Meanwhile, reconfigurable processors and emerging FPGA computing devices are also widely used. However, the research of mobile GPU for general computing cooperation with FPGA, is still scarce. Such heterogeneous systems pose a great challenge to the parallel programming. In this paper, we present a Flow-Lead-In Architecture (FLIA) is proposed as a unified data flow driven development model based on coupled GPU-FPGA. The servant represents an intermediate language module that is compiled from the high-level programming language and is compiled to different types of processors at runtime. Execution-flow abstracts the communication task between the servants and controls the pipeline execution for spatial parallelism. By scheduling multiple servants to heterogeneous processors, the cooperation system uses fewer resources to achieve near performance and power with the pure FPGA system.
    Keywords: heterogeneous computing; GPU-FPGA cooperation; mobile GPU; ARM GPU FPGA partitioning; reconfigurable computing.

  • FPGA Implementations of Fruit-v2, Fruit-80 and Grain-128AEAD Stream Ciphers   Order a copy of this article
    by Guntapudi Vamsi Krishna, Dheeraj Kumar Sharma 
    Abstract: The use of limited resources devices such as WSN, RFID, IIOT has increased. Xilinx FPGA solutions, provide real-time processing and flexibility. For all these, the main challenging problem is confidentially with limited resources. eSTREAM portfolio was started to discover the efficient lightweight stream ciphers. Later on, various stream ciphers have been proposed depending upon the requirement of applications. The minimum area, higher frequency, and higher throughput-area ratio are the main requirements. This can be achieved by implementing ciphers in three ways i.e., basic version, serial version, and parallel version. Using the basic version, one can achieve a higher operating frequency. The lesser area can be accomplished in the serial version. In parallel version, the maximum throughput-area ratio is obtained. This paper discusses the design and implementation of the basic version, serial version, and parallel version of Fruit-v2, Fruit-80, and Grain-128AEAD. The main objective is to achieve the requirement based on the application.
    Keywords: FPGA; Stream Cipher; Ultra-lightweight; LFSR; NLFSR; Basic Version; Serial Version; Parallel Version.

  • Design and Verification of ARM Watchdog Timer using UVM   Order a copy of this article
    by Ragamathana R, Prathiba Ashok, Shaik Chand Basha 
    Abstract: Watchdog Timer is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-chip peripheral. It is an AMBA slave module and connects to the Advanced Peripheral Bus (APB). It consists of a 32-bit down counter with a programmable timeout interval which generates an interrupt and applies reset to the processor on time out. Verification IP(Intellectual Property) is a smart way to verify the functional correctness of any complex design. This is achieved by Constrained Random Verification (CRV) which generates legal test scenarios randomly that weed out the bugs and corner cases thereby validating the characteristic features of watchdog timer. CRV also builds automated checkers and provides higher coverage goals. In this work, ARM Watchdog Timer is designed in verilog and System-on-chip level verification of the same is performed using Universal Verification Methodology (UVM) by combining both Constrained Random Verification and Coverage Driven Verification (CDV) to ensure its functional correctness.
    Keywords: Advanced Microcontroller Bus Architecture; Advanced Peripheral Bus; Watchdog Timer IP; verification IP; Universal Verification Methodology; System-on-chip level verification; Constrained Random Verification; Coverage Driven Verification.

  • Multistage Pipelined Architectures of Piccolo cipher for High-Speed IoT Applications   Order a copy of this article
    by Shubham Mishra, Zeesha Mishra, Saroj Kumar Panigrahy, Bibhudendra Acharya 
    Abstract: The lightweight cryptography has been an obsession in recent times because of the rising security concerns in the field of smart connected devices having low resource prerequisites in IoT applications. The number of connected devices in IoT applications, has been increasing, throughout leaving severe security concerns. Result comparisons have been made with different block ciphers using 6-input and 4-input LUTs of proposed work, which has been implemented for high-speed IoT and RFID application. This work has architectures which give 257% improvement for throughput per area and 21.9% improvement in area with other efficient architectures. Architectures have been implemented using multistage pipelined method in critical paths. Proposed architectures of Piccolo-80, and Piccolo-128 has provided the speed in terms of throughput as 1288.4 Mbps, 1046.1 Mbps and Mbps respectively on FPGA platform. The proposed designs are also implemented in ASIC 0.18 ?m UMC technology in which Piccolo-80 and Piccolo-128 have an frequency of 714.28 and 649 MHz respectively.
    Keywords: IoT; FPGA; Throughput; Feistel structure; Cryptography; RFID; Piccolo; ASIC; Gate Equivalent.

  • Real-time performance analysis of distributed multithreaded applications in a cluster of ARM-based embedded devices   Order a copy of this article
    by George K. Adam 
    Abstract: The challenges in real-time cluster computing, particularly in computing efficiency and reliability have evolved significantly due to the increase of IoT, cloud and edge computing applications. Lately a number of low-power and low-cost clusters have appeared, based upon single board computers, which deploy multithreading techniques to run in parallel thousands of tasks, to support the ever-increasing demand for timely data processing. However, their real-time performance is still under research. This paper proposes a real-time performance analysis approach in evaluating metrics such as threads execution time, response time, parallel efficiency and speedup. The measurements are based upon recursively generated multithreaded applications running in parallel and distributed in multiple cores within a cluster of Raspberry Pi4, running Linux with real-time support, interconnected on a fast gigabit Ethernet. The experimental results validate the efficiency of the proposed approach and show that real-time support enables higher throughput across all workloads, and lower execution times.
    Keywords: cluster computing; real-time; performance analysis; multithreaded applications; embedded devices.

Special Issue on: Recent Advances on High Performance Memetic Algorithms

  • Countermeasure SDN-based IoT Threats Using Blockchain Multicontroller   Order a copy of this article
    by Janani Kariyappa, Ramamoorthy S 
    Abstract: IoT is making significant progress in a variety of fields, including healthcare, smart grids, supply chains, and so on. It also makes people's daily lives easier and improves their interactions with one another and with their surroundings and environment. In the Internet of Things, issues including security, comparability, power consumption, and device heterogeneity have been around for a long time. Due to the limited computational and energy capabilities of networked systems, security and power considerations play a crucial role in data transfer via IoT and edge systems. Software-defined networks with multiple controllers have become popular because they make it easier to manage large networks. But they are open to a number of attacks, such as false data injection, which makes controller topologies inconsistent. To solve this problem, we suggest a multicontroller blockchain for SDN network, a security architecture that combines blockchain and multicontroller SDN and divides the network into several domains. We put forth a blockchain-based solution. SDN multi-controller model for secure and power-efficient IoT networks. Every SDN domain is run by one master controller, who talks to the other domain masters through the blockchain. Master controllers produce blocks of network flow updates, and redundant controllers evaluate them using a reputation system. The reputation system ranks block creators and voters after each vote, utilising constant and adaptive fading reputation mechanisms. The assessment findings show rapid and excellent fraud protection. There is also a blockchain-enabled SDN multi-controller architecture for IoT networks that uses a clustering algorithm and a new routing protocol that is both secure and energy-efficient. Experimental results indicate that the cluster-based routing protocol has a greater capacity, a shorter response time, and a lower overall power requirement than other protocols. It has been shown that our proposed architecture outperforms the classic blockchain.
    Keywords: IoT Security; Multi-Controller Blockchain; Power Consumption; Software Defined Network multi-controller.