
International Journal of High Performance Systems Architecture
2011 Vol.3 No.1
Special Issue on Network-On-Chip and Reconfigurable Computing
Guest Editor: Professor Nader Bagherzadeh
Pages | Title and author(s) |
2-11 | A networks-on-chip emulation/verification frameworkPeng Liu, Yangfan Liu, Bingjie Xia, Chunchang Xiang, Xiaohang Wang, Kejun Wu, Weidong Wang, Qingdong Yao DOI: 10.1504/IJHPSA.2011.038053 |
12-22 | A scheduling approach for distributed resource architectures with scarce communication resourcesAkira Hatanaka, Nader Bagherzadeh DOI: 10.1504/IJHPSA.2011.038054 |
23-32 | A unified design space simulation environment for network-on-chip: fuse-NAshwini Raina, Venkatesan Muthukumar DOI: 10.1504/IJHPSA.2011.038055 |
33-40 | Reconfigurable processor based on ALU array architecture for software radioMakoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka, Shin-ichiro Tomisawa DOI: 10.1504/IJHPSA.2011.038056 |
Additional Papers |
41-55 | PRADA: a high-performance reconfigurable parallel architecture based on the dataflow modelEdson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Mauricio Perretto DOI: 10.1504/IJHPSA.2011.038057 |
56-63 | Electromigration-aware dynamic routing algorithm for network-on-chip applicationsAmir Hosseini, Vahid Shabro DOI: 10.1504/IJHPSA.2011.038058 |