International Journal of High Performance Computing and Networking
2004 Vol.2 No.1
Pages | Title and author(s) |
1-10 | Future ILP processorsAdrian Cristal, Josep Llosa, Mateo Valero, Daniel Ortega DOI: 10.1504/IJHPCN.2004.009263 |
11-21 | A latency-conscious SMT branch prediction architectureAyose Falcon, Oliverio J. Santana, Alex Ramirez, Mateo Valero DOI: 10.1504/IJHPCN.2004.009264 |
22-35 | Dynamic tiling for effective use of shared caches on multithreaded processorsDimitrios S. Nikolopoulos DOI: 10.1504/IJHPCN.2004.009265 |
36-44 | High-speed parallel external sorting of data with arbitrary distributionMinsoo Jeon, Dongseung Kim DOI: 10.1504/IJHPCN.2004.009266 |
45-54 | Optimising long-latency-load-aware fetch policies for SMT processorsFrancisco J. Cazorla, Alex Ramirez, Mateo Valero, Enrique Fernandez DOI: 10.1504/IJHPCN.2004.009267 |
55-64 | Bounding the minimal completion time in high-performance parallel processingLars Lundberg, Magnus Broberg, Kamilla Klonowska DOI: 10.1504/IJHPCN.2004.009268 |