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International Journal of High Performance Systems Architecture

2011 Vol. 3 No. 1

Special Issue on Network-On-Chip and Reconfigurable Computing

Guest Editor: Professor Nader Bagherzadeh

 

Introduction
PagesTitle and authors
2-11A networks-on-chip emulation/verification framework
Peng Liu, Yangfan Liu, Bingjie Xia, Chunchang Xiang, Xiaohang Wang, Kejun Wu, Weidong Wang, Qingdong Yao
DOI: 10.1504/IJHPSA.2011.038053

12-22A scheduling approach for distributed resource architectures with scarce communication resources
Akira Hatanaka, Nader Bagherzadeh
DOI: 10.1504/IJHPSA.2011.038054

23-32A unified design space simulation environment for network-on-chip: fuse-N
Ashwini Raina, Venkatesan Muthukumar
DOI: 10.1504/IJHPSA.2011.038055

33-40Reconfigurable processor based on ALU array architecture for software radio
Makoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka, Shin-ichiro Tomisawa
DOI: 10.1504/IJHPSA.2011.038056

Additional Papers

41-55PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model
Edson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Mauricio Perretto
DOI: 10.1504/IJHPSA.2011.038057

56-63Electromigration-aware dynamic routing algorithm for network-on-chip applications
Amir Hosseini, Vahid Shabro
DOI: 10.1504/IJHPSA.2011.038058