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Vol. 2
Vol. 1

International Journal of High Performance Computing and Networking

2004 Vol. 2 No. 1


PagesTitle and authors
1-10Future ILP processors
Adrian Cristal, Josep Llosa, Mateo Valero, Daniel Ortega
DOI: 10.1504/IJHPCN.2004.009263

11-21A latency-conscious SMT branch prediction architecture
Ayose Falcon, Oliverio J. Santana, Alex Ramirez, Mateo Valero
DOI: 10.1504/IJHPCN.2004.009264

22-35Dynamic tiling for effective use of shared caches on multithreaded processors
Dimitrios S. Nikolopoulos
DOI: 10.1504/IJHPCN.2004.009265

36-44High-speed parallel external sorting of data with arbitrary distribution
Minsoo Jeon, Dongseung Kim
DOI: 10.1504/IJHPCN.2004.009266

45-54Optimising long-latency-load-aware fetch policies for SMT processors
Francisco J. Cazorla, Alex Ramirez, Mateo Valero, Enrique Fernandez
DOI: 10.1504/IJHPCN.2004.009267

55-64Bounding the minimal completion time in high-performance parallel processing
Lars Lundberg, Magnus Broberg, Kamilla Klonowska
DOI: 10.1504/IJHPCN.2004.009268