International Journal of High Performance Systems Architecture
2013 Vol.4 No.3
Pages | Title and author(s) |
121-131 | FPGA architecture for pairwise statistical significance estimationDaniel Honbo; Amit Pande; Alok Choudhary DOI: 10.1504/IJHPSA.2013.055222 |
132-143 | Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processingAmir Gargouri; Mohamed Krid; Dorra Sellami Masmoudi DOI: 10.1504/IJHPSA.2013.055224 |
144-166 | Reconfigurable hardware for fuzzy controllerPaulo Renato de Souza Silva Sandres; Nadia Nedjah; Luiza de Macedo Mourelle DOI: 10.1504/IJHPSA.2013.055225 |
167-182 | Modern flash technologies: a flash translation layer perspectiveYoonsuk Choi; Shahram Latifi DOI: 10.1504/IJHPSA.2013.055252 |