
International Journal of Circuits and Architecture Design
2016 Vol.2 No.2
Pages | Title and author(s) |
105-117 | Low-power smart passive REU for industrial IoT applicationsVyasa Sai; Marlin H. Mickle DOI: 10.1504/IJCAD.2016.10003035 |
118-131 | GF(2m) versatile multiplier/adder architecture for cryptographic applicationsHaichour Amina Selma; Hamadouche M'hamed DOI: 10.1504/IJCAD.2016.10003046 |
132-141 | Design of new NAND/NOR gates in QCA using single electron cellsZeynab Namakizadeh Esfahani; Mahya Sam; Keivan Navi DOI: 10.1504/IJCAD.2016.10003034 |
142-154 | 0.5 V, 5 MHz active-RC biquad filter in 90 nm CMOS technologyS. Rekha; T. Laxminidhi DOI: 10.1504/IJCAD.2016.10003036 |
155-168 | Effectiveness of body bias and hybrid logic: an energy efficient approach to design adders in sub-threshold regimePriya Gupta; Ishan Munje; Anu Gupta; Abhijit Asati DOI: 10.1504/IJCAD.2016.10003038 |
169-181 | Design of PVT compensated current starved ring oscillatorD. Anitha; K. Manjunatha Chari; P. Satish Kumar DOI: 10.1504/IJCAD.2016.10003051 |