Forthcoming and Online First Articles

International Journal of Circuits and Architecture Design

International Journal of Circuits and Architecture Design (IJCAD)

Forthcoming articles have been peer-reviewed and accepted for publication but are pending final changes, are not yet published and may not appear here in their final order of publication until they are assigned to issues. Therefore, the content conforms to our standards but the presentation (e.g. typesetting and proof-reading) is not necessarily up to the Inderscience standard. Additionally, titles, authors, abstracts and keywords may change before publication. Articles will not be published until the final proofs are validated by their authors.

Forthcoming articles must be purchased for the purposes of research, teaching and private study only. These articles can be cited using the expression "in press". For example: Smith, J. (in press). Article Title. Journal Title.

Articles marked with this shopping trolley icon are available for purchase - click on the icon to send an email request to purchase.

Online First articles are published online here, before they appear in a journal issue. Online First articles are fully citeable, complete with a DOI. They can be cited, read, and downloaded. Online First articles are published as Open Access (OA) articles to make the latest research available as early as possible.

Open AccessArticles marked with this Open Access icon are Online First articles. They are freely available and openly accessible to all without any restriction except the ones stated in their respective CC licenses.

Register for our alerting service, which notifies you by email when new issues are published online.

We also offer which provide timely updates of tables of contents, newly published articles and calls for papers.

International Journal of Circuits and Architecture Design (3 papers in press)

Regular Issues

  • Automated design and multi-objective optimization of low-power CMOS digital integrated circuits using genetic algorithm   Order a copy of this article
    by Afrouz Narimani 
    Abstract: In this article an automated design algorithm for transistor sizing of CMOS digital integrated circuits based on Genetic Algorithm (GA) is presented. The proposed designed algorithm is developed in MATLAB in which two performance factors including propagation delay and power consumption are considered as fitness functions. Additionally, proposed circuit is simulated by HSPICE using 50nm CMOS technology to compare the results of the proposed design algorithm. Moreover, the Pareto optimal solution is implemented for multi-objective optimization of both objectives (power consumption and propagation delay). However, as it is shown in the paper, simulation results properly come to an agreement with MATLAB analytical results which imply the acceptable results and performance of the proposed design algorithm. The performance of the proposed approach has been evaluated by applying on CMOS Full-Adder as a result the power-delay product (PDP) reduce approximately 50 percent in comparison with other designs.
    Keywords: Genetic Algorithm; VLSI; Digital Integrated Circuits; Propagation delay; Power consumption; CMOS.

  • Design of High Speed and Low Power Multiplier using Dual-Mode Square Adder   Order a copy of this article
    by B. Jaya Lakshmi, R. Ramana Reddy, Naresh K. Darimireddy 
    Abstract: Adders are the basic building blocks in analogue and digital circuits for implementing arithmetic operations. Different adder designs are reported to obtain high speed, less area and low power dissipation. Dual mode logic (DML) and dual mode addition (DMADD) techniques can be used to achieve low power and high speed addition. Adders are the main blocks in multipliers. In this paper Braun multiplier is implemented using dual-mode (DM) square adder. The DM square adder architecture is a combination of DML and DMADD techniques. By incorporating the DM square adder in processors, power dissipation can be reduced. The full adder used in dual-mode square adder is static energy recovery full (SERF) adder which is faster and consumes less power compared to conventional full adder. For Braun multiplier using DM square adder power consumption is reduced by 63.54% and speed is increased by 90%. The proposed designs are implemented using mentor graphics tools in 130 nm technology.
    Keywords: dual mode logic; DML; dual mode addition; DMADD; DM square adder; SERF adder; Braun multiplier; low power.
    DOI: 10.1504/IJCAD.2019.10024523
     
  • Wireless constant current control circuit for LED light source in PSD test system   Order a copy of this article
    by Xiaohong Lu, Yihan Luan, Feixiang Ruan, Pengrong Hou, Xudong Hao 
    Abstract: Considering the complexity of the actuators movement to be tested, the target light source in the PSD test system must be driven by a constant current and wirelessly controlled. In this paper, the high-power LED point light source with high electro-optic conversion efficiency is used as the target light source to provide sufficient optical power. The lithium battery and constant current drive circuit are used to supply power to the LED, which ensures the stability and service life of the light source. The working state of the drive circuit is controlled by the wireless digital transmission module. High-capacity Lithium battery pack provides power to the constant current drive circuit and the wireless digital transmission module. The involved LED light source and its control circuit have the advantages of fast response, short time of state switching process, good stability of light source and long endurance.
    Keywords: PSD; LED; constant current; wireless; circuit.
    DOI: 10.1504/IJCAD.2020.10031356