International Journal of Circuits and Architecture Design
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International Journal of Circuits and Architecture Design (1 paper in press)
Automated design and multi-objective optimization of low-power CMOS digital integrated circuits using genetic algorithm by Afrouz Narimani Abstract: In this article an automated design algorithm for transistor sizing of CMOS digital integrated circuits based on Genetic Algorithm (GA) is presented. The proposed designed algorithm is developed in MATLAB in which two performance factors including propagation delay and power consumption are considered as fitness functions. Additionally, proposed circuit is simulated by HSPICE using 50nm CMOS technology to compare the results of the proposed design algorithm. Moreover, the Pareto optimal solution is implemented for multi-objective optimization of both objectives (power consumption and propagation delay). However, as it is shown in the paper, simulation results properly come to an agreement with MATLAB analytical results which imply the acceptable results and performance of the proposed design algorithm. The performance of the proposed approach has been evaluated by applying on CMOS Full-Adder as a result the power-delay product (PDP) reduce approximately 50 percent in comparison with other designs. Keywords: Genetic Algorithm; VLSI; Digital Integrated Circuits; Propagation delay; Power consumption; CMOS.