Forthcoming articles

International Journal of Circuits and Architecture Design

International Journal of Circuits and Architecture Design (IJCAD)

These articles have been peer-reviewed and accepted for publication but are pending final changes, are not yet published and may not appear here in their final order of publication until they are assigned to issues. Therefore, the content conforms to our standards but the presentation (e.g. typesetting and proof-reading) is not necessarily up to the Inderscience standard. Additionally, titles, authors, abstracts and keywords may change before publication. Articles will not be published until the final proofs are validated by their authors.

Forthcoming articles must be purchased for the purposes of research, teaching and private study only. These articles can be cited using the expression "in press". For example: Smith, J. (in press). Article Title. Journal Title.

Articles marked with this shopping trolley icon are available for purchase - click on the icon to send an email request to purchase.

Register for our alerting service, which notifies you by email when new issues are published online.

Open AccessArticles marked with this Open Access icon are freely available and openly accessible to all without any restriction except the ones stated in their respective CC licenses.
We also offer which provide timely updates of tables of contents, newly published articles and calls for papers.

International Journal of Circuits and Architecture Design (1 paper in press)

Regular Issues

  • Automated design and multi-objective optimization of low-power CMOS digital integrated circuits using genetic algorithm   Order a copy of this article
    by Afrouz Narimani 
    Abstract: In this article an automated design algorithm for transistor sizing of CMOS digital integrated circuits based on Genetic Algorithm (GA) is presented. The proposed designed algorithm is developed in MATLAB in which two performance factors including propagation delay and power consumption are considered as fitness functions. Additionally, proposed circuit is simulated by HSPICE using 50nm CMOS technology to compare the results of the proposed design algorithm. Moreover, the Pareto optimal solution is implemented for multi-objective optimization of both objectives (power consumption and propagation delay). However, as it is shown in the paper, simulation results properly come to an agreement with MATLAB analytical results which imply the acceptable results and performance of the proposed design algorithm. The performance of the proposed approach has been evaluated by applying on CMOS Full-Adder as a result the power-delay product (PDP) reduce approximately 50 percent in comparison with other designs.
    Keywords: Genetic Algorithm; VLSI; Digital Integrated Circuits; Propagation delay; Power consumption; CMOS.