International Journal of High Performance Systems Architecture
2017 Vol.7 No.2
Pages | Title and author(s) |
57-69 | A VLSI architecture of CORDIC-based popular windows and its FPGA prototypeVikas Kumar; Kailash C. Ray; Preetam Kumar DOI: 10.1504/IJHPSA.2017.087156 |
70-86 | Synthesis of standard functions and generic Ex-OR module using layered T gateChiradeep Mukherjee; Saradindu Panda; Asish Kumar Mukhopadhyay; Bansibadan Maji DOI: 10.1504/IJHPSA.2017.087164 |
87-97 | An enhanced model for reliable deflection routing in mesh network on chipSimi Zerine Sleeba; M.G. Mini DOI: 10.1504/IJHPSA.2017.087166 |
98-104 | Partial dynamic reconfiguration framework for FPGAs through remote accessA. Anitha; M. Madhavi Latha DOI: 10.1504/IJHPSA.2017.087179 |
105-112 | Capacity planning of the registration server in cloud storageRui Gu; Shunfu Jin; Haixing Wu DOI: 10.1504/IJHPSA.2017.087183 |