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International Journal of High Performance Systems Architecture

2015 Vol. 5 No. 4

 

PagesTitle and authors
193-201A novel low-energy CNFET-based full adder cell using pass-transistor logic
Yavar Safaei Mehrabani; Reza Faghih Mirzaee; Mohammad Eshghi
DOI: 10.1504/IJHPSA.2015.072846

202-208New fully single layer QCA full-adder cell based on feedback model
Somaye Mohammadyan; Shaahin Angizi; Keivan Navi
DOI: 10.1504/IJHPSA.2015.072847

209-215High-performance ternary logic gates for nanoelectronics
Mohammad Hossein Moaiyeri; Mohsen Shamohammadi; Fazel Sharifi; Keivan Navi
DOI: 10.1504/IJHPSA.2015.072850

216-227A small and power efficient checkpoint core architecture for manycore processors
Mageda Sharafeddin; Haitham Akkary
DOI: 10.1504/IJHPSA.2015.072852

228-239XEMU: a cross-ISA full-system emulator on multiple processor architectures
Huang Wang; Chao Wang; Huaping Chen
DOI: 10.1504/IJHPSA.2015.072853

240-251Dynamic communications mapping in multi-tasks NoC-based heterogeneous MPSoCs platform
Mohammed Kamel Benhaoua; Amit Kumar Singh
DOI: 10.1504/IJHPSA.2015.072856