International Journal of High Performance Systems Architecture
2015 Vol.5 No.4
Pages | Title and author(s) |
193-201 | A novel low-energy CNFET-based full adder cell using pass-transistor logicYavar Safaei Mehrabani; Reza Faghih Mirzaee; Mohammad Eshghi DOI: 10.1504/IJHPSA.2015.072846 |
202-208 | New fully single layer QCA full-adder cell based on feedback modelSomaye Mohammadyan; Shaahin Angizi; Keivan Navi DOI: 10.1504/IJHPSA.2015.072847 |
209-215 | High-performance ternary logic gates for nanoelectronicsMohammad Hossein Moaiyeri; Mohsen Shamohammadi; Fazel Sharifi; Keivan Navi DOI: 10.1504/IJHPSA.2015.072850 |
216-227 | A small and power efficient checkpoint core architecture for manycore processors Mageda Sharafeddin; Haitham Akkary DOI: 10.1504/IJHPSA.2015.072852 |
228-239 | XEMU: a cross-ISA full-system emulator on multiple processor architecturesHuang Wang; Chao Wang; Huaping Chen DOI: 10.1504/IJHPSA.2015.072853 |
240-251 | Dynamic communications mapping in multi-tasks NoC-based heterogeneous MPSoCs platformMohammed Kamel Benhaoua; Amit Kumar Singh DOI: 10.1504/IJHPSA.2015.072856 |