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Vol. 2
Vol. 1

International Journal of High Performance Systems Architecture

2009 Vol. 2 No. 1


PagesTitle and authors
1-15High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC
D. Meganathan, Raja Paul Perinbam, R. Deepalakshmi
DOI: 10.1504/IJHPSA.2009.030094

16-25Context-oriented exception handling
Fabiane Cristine Dillenburg, Jorge Luis Victoria Barbosa
DOI: 10.1504/IJHPSA.2009.030095

26-34A massively parallel hardware architecture for ray-tracing
A.S. Nery, N. Nedjah, F.M.G. Franca
DOI: 10.1504/IJHPSA.2009.030096

35-45Dual channel addition based FFT processor architecture for signal and image processing
Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta
DOI: 10.1504/IJHPSA.2009.030097

46-57Efficient mapping of an image processing application for a network-on-chip based implementation
Marcus Vinicius Carvalho Da Silva, Nadia Nedjah, Luiza de Macedo Mourelle
DOI: 10.1504/IJHPSA.2009.030098

58-67HieraAnalyses – a tool for hierarchical analysis of parallel programs
Thatyana de Faria Piola Seraphim, Enzo Seraphim, Gonzalo Travieso
DOI: 10.1504/IJHPSA.2009.030099