Enhanced parallel CFAR architecture with sharing resources using FPGA
by Sadok Msadaa; Youness Lahbib; Ridha Djemal; Abdelkader Mami
International Journal of Embedded Systems (IJES), Vol. 14, No. 1, 2021

Abstract: The real time CFAR processor needs a very high computational performance. To meet with the real-time requirements, this paper presents an implementation of a new hardware parallel design using ACOSD-CFAR detector. The aim of this work is to increase the architecture throughput and decrease the power consumption while maintaining a high resolution target detection. Our proposed implementation exploits the properties of the ACOSD-CFAR detector to enhance it with a parallel architecture include some sharing resources. Compared to conventional implementation of CFAR, the proposed architecture increases the throughput from 2,576 Mbit/s to 4,736 Mbit/s by 184% and reduces the power consumption by 15%. The design is implemented on a Zync 7000 FPGA board, which is considered as a common validation platform.

Online publication date: Tue, 22-Dec-2020

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Embedded Systems (IJES):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com