Authors: Sadok Msadaa; Youness Lahbib; Ridha Djemal; Abdelkader Mami
Addresses: Faculty of Mathematical, Physical, and Natural Sciences of Tunis, FST, Campus Universitaire El-Manar, 2092 El Manar Tunis, Tunisia ' National Engineering School of Carthage, 45 Rue des Entrepreneurs 2035 Charguia II, Tunis-Carthage-Tunisie, Tunisia ' College of Engineering, King Saoud University, Saudi Arabia ' Faculty of Mathematical, Physical, and Natural Sciences of Tunis, FST, Campus Universitaire El-Manar, 2092 El Manar Tunis, Tunisia
Abstract: The real time CFAR processor needs a very high computational performance. To meet with the real-time requirements, this paper presents an implementation of a new hardware parallel design using ACOSD-CFAR detector. The aim of this work is to increase the architecture throughput and decrease the power consumption while maintaining a high resolution target detection. Our proposed implementation exploits the properties of the ACOSD-CFAR detector to enhance it with a parallel architecture include some sharing resources. Compared to conventional implementation of CFAR, the proposed architecture increases the throughput from 2,576 Mbit/s to 4,736 Mbit/s by 184% and reduces the power consumption by 15%. The design is implemented on a Zync 7000 FPGA board, which is considered as a common validation platform.
Keywords: CFAR; VHDL; radar; parallel; FPGA; ACOSD; radar detector; radar implantation; enhanced; radar architecture; sharing resource.
International Journal of Embedded Systems, 2021 Vol.14 No.1, pp.45 - 53
Received: 13 Dec 2018
Accepted: 02 Sep 2019
Published online: 22 Dec 2020 *