Title: Generating verifiable LOTOS specifications from UML models: a graph transformation-based approach

Authors: Salim Djaaboub; Elhillali Kerkouche; Allaoua Chaoui

Addresses: MISC Laboratory, Department of Computer Science and its Applications, Faculty of NTIC, University Constantine 2, Constantine, Algeria ' Department of Computer Science, University of Jijel, Algeria; MISC Laboratory, University Constantine 2, Constantine, Algeria ' MISC Laboratory, Department of Computer Science and its Applications, Faculty of NTIC, University Constantine 2, Constantine, Algeria

Abstract: The increasing complexity and widespread use of complex and critical systems require advanced techniques and tools to address their specification, verification and validation. The goal of this paper is to integrate two standard languages (UML and LOTOS) for the specification, verification and validation of dynamic behaviours of critical systems. The main purpose of this integration is to take benefits of the ease-of-use of the graphical notation of UML in system modelling and the formal notation of LOTOS in system verification. In this paper, we propose a graph transformation-based approach to generate automatically LOTOS specifications from UML dynamic models. This approach enables developers, in one hand to model the behaviours of systems using graphical UML statechart and communication diagrams, and in the other hand to generate automatically verifiable LOTOS specifications. The proposed approach is automated using AToM³ tool, and it is illustrated through the modelling and verification of two embedded systems.

Keywords: unified modelling language; UML; LOTOS; statechart diagram; communication diagram; critical systems; formal methods; verification; graph transformation; AToM³.

DOI: 10.1504/IJES.2018.095751

International Journal of Embedded Systems, 2018 Vol.10 No.6, pp.453 - 469

Received: 22 Mar 2016
Accepted: 03 Oct 2016
Published online: 22 Oct 2018 *

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