Title: Intrinsic I-V and C-V characteristics of ultra-thin oxide MOS (p) and MOS (n) structures under deep depletion

Authors: Yu-Ching Liao; Jenn-Gwo Hwu

Addresses: Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan ' Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan

Abstract: Ultra-thin oxide MOS (p) and MOS (n) capacitors were used in this study to discuss their intrinsic I-V and C-V characteristics under deep depletion. Through deep depletion analysis proposed by Cheng and Hwu [1], we found that the gate leakage current of MOS (p) was perimeter-dependent while MOS (n) was area-dependent. These suggest a strong indication of Schottky barrier height lowering for holes in MOS (p) owing to larger voltage drop on oxide at edge region as the result of fringing field effect [2]. Furthermore, MOS (p) and MOS (n) were put under illumination to investigate the non-uniform movement of minority carriers. As expected, minority carriers of MOS (n) have shorter response time because of comprehensive tunnelling current comparing to MOS (p). A thorough understanding of MOS (p) and MOS (n) under deep depletion was presented. In addition, deep depletion as a tool to investigate the oxide quality was demonstrated.

Keywords: ultra-thin oxide; MOS capacitors; p substrate; n substrate; deep depletion; Schottky barrier; fringing field; gate leakage current; oxide quality.

DOI: 10.1504/IJNT.2015.066190

International Journal of Nanotechnology, 2015 Vol.12 No.1/2, pp.11 - 26

Published online: 04 Dec 2014 *

Full-text access for editors Access for subscribers Purchase this article Comment on this article