Authors: Bojan Jovanović; Milun Jevtić
Addresses: Department of Electronics, Faculty of Electronic Engineering, University of Niš, A. Medvedeva 14, 18000 Niš, Serbia. ' Department of Electronics, Faculty of Electronic Engineering, University of Niš, A. Medvedeva 14, 18000 Niš, Serbia
Abstract: The continued scaling of the CMOS technology has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. In this paper, we present some widely used techniques for static and dynamic power minimisation in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the design's architectural variations. Along with the overview of power minimisation techniques, as an example, the circuit of binary divider was introduced and implemented in various families FPGAs to demonstrate technological as well as Placement and Routing (PAR) influence on total power consumption.
Keywords: static power consumption; dynamic power consumption; power minimisation; binary divider; FPGA; field programmable gate arrays; VLSI circuits.
International Journal of Reasoning-based Intelligent Systems, 2012 Vol.4 No.1/2, pp.46 - 57
Available online: 10 Apr 2012 *Full-text access for editors Access for subscribers Purchase this article Comment on this article