Title: Reconfiguration support for vector operations

Authors: Hongyan Yang, Sotirios G. Ziavras, Jie Hu

Addresses: Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA. ' Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA. ' Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA

Abstract: A programmable vector processor and its implementation on a Field-Programmable Gate Array (FPGA) board are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor runs at 70 MHz on the Xilinx XC2V6000-5 chip. FPGA resource utilisation information is included in this paper. To test the performance, the W-matrix sparse solver for linear equations is realised on this platform. W-matrix was first proposed for power flow analysis and is prone to parallel computing. We show that actual power matrices with up to 1723 nodes can be dealt with in less than 1.1 ms on the FPGA. A comparison with a commercial PC indicates that the vector processor is very competitive for such computation-intensive problems.

Keywords: system-on-a-chip; SOC; field programmable gate array; FPGA; vector processors; W-matrix method; matrix sparsity; linear equation solver; reconfiguration support.

DOI: 10.1504/IJHPSA.2007.015394

International Journal of High Performance Systems Architecture, 2007 Vol.1 No.2, pp.89 - 97

Published online: 14 Oct 2007 *

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