Reconfiguration support for vector operations
by Hongyan Yang, Sotirios G. Ziavras, Jie Hu
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 1, No. 2, 2007

Abstract: A programmable vector processor and its implementation on a Field-Programmable Gate Array (FPGA) board are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor runs at 70 MHz on the Xilinx XC2V6000-5 chip. FPGA resource utilisation information is included in this paper. To test the performance, the W-matrix sparse solver for linear equations is realised on this platform. W-matrix was first proposed for power flow analysis and is prone to parallel computing. We show that actual power matrices with up to 1723 nodes can be dealt with in less than 1.1 ms on the FPGA. A comparison with a commercial PC indicates that the vector processor is very competitive for such computation-intensive problems.

Online publication date: Sun, 14-Oct-2007

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