Novel design of nanometric reversible floating point adder with parity preservation capability
by Parisa Tabatabaii; Majid Haghparast
International Journal of Innovative Computing and Applications (IJICA), Vol. 7, No. 2, 2016

Abstract: Reversible logic is a new theme of study that requires reversible logic circuits and plays a vital role in quantum computing, low power CMOS and nanotechnology. Parity preserving is one of the oldest procedures for the extension of fault tolerant systems. Floating-point addition is one of the most complicated computer arithmetic operations. There are many reversible implementations of logical and arithmetic units like ALU, multiplier, adder, etc., but few designs for reversible floating-point adder exist. In this paper, we present parity preserving reversible floating-point adder design with nanometric scale for the first time. Also, we present a parity preserving reversible gate. At the end, the final results are reported. All the scales are in nanometric area.

Online publication date: Wed, 06-Jul-2016

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