Reconfigurable multi-core architecture - a plausible solution to the von Neumann performance bottleneck
by Chun-Hsien Lu; Chih-Sheng Lin; Hung-Lin Chao; Jih-Sheng Shen; Pao-Ann Hsiung
International Journal of Adaptive and Innovative Systems (IJAIS), Vol. 2, No. 3, 2015

Abstract: The ill-famed von Neumann bottleneck has been the main performance hurdle since the invention of computers. Although several techniques such as separate data/instruction caches, branch prediction, and parallel computing have been proposed and improved efficiency, the throughput bottleneck between CPU and memory is still very much there. We propose a novel reconfigurable multi-core architecture (RMA) to address this issue via the dynamic allocation of heterogeneous computing resources and distributed memory. We show how this is feasible with the state-of-the-art technologies of dynamic partial reconfiguration of hardware resources and runtime operating system configuration. Experiments and analysis show how RMA alleviates the performance bottleneck.

Online publication date: Thu, 28-Jan-2016

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Adaptive and Innovative Systems (IJAIS):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com