Title: Reconfigurable multi-core architecture - a plausible solution to the von Neumann performance bottleneck
Authors: Chun-Hsien Lu; Chih-Sheng Lin; Hung-Lin Chao; Jih-Sheng Shen; Pao-Ann Hsiung
Addresses: Department of Computer Science and Information Engineering, National Chung Cheng University, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, Taiwan ' Department of Computer Science and Information Engineering, National Chung Cheng University, Taiwan
Abstract: The ill-famed von Neumann bottleneck has been the main performance hurdle since the invention of computers. Although several techniques such as separate data/instruction caches, branch prediction, and parallel computing have been proposed and improved efficiency, the throughput bottleneck between CPU and memory is still very much there. We propose a novel reconfigurable multi-core architecture (RMA) to address this issue via the dynamic allocation of heterogeneous computing resources and distributed memory. We show how this is feasible with the state-of-the-art technologies of dynamic partial reconfiguration of hardware resources and runtime operating system configuration. Experiments and analysis show how RMA alleviates the performance bottleneck.
Keywords: reconfigurable architecture; memory synthesis; FPGA; field-programmable gate arrays; reconfiguration; multi-core architecture; von Neumann bottleneck; performance bottleneck; throughput bottleneck; dynamic resource allocation; computing resources; distributed memory.
DOI: 10.1504/IJAIS.2015.074399
International Journal of Adaptive and Innovative Systems, 2015 Vol.2 No.3, pp.217 - 231
Received: 25 Nov 2013
Accepted: 21 Jul 2014
Published online: 28 Jan 2016 *