An efficient arbitration technique for system-on-chip communications Online publication date: Sat, 21-Jun-2014
by Ruchi Gautam; Mohammad Ayoub Khan
International Journal of Circuits and Architecture Design (IJCAD), Vol. 1, No. 2, 2014
Abstract: The increasing demand of applications in consumer electronics has increased the number of computing resources in single-chip. The traditional communication architecture in SoC is not capable to address the increasing bandwidth requirements of future large systems. Therefore, network-on-chip (NoC) has emerged as an interconnection architecture and communication paradigm for increasingly complex on-chip networks. The role of bus and arbitration logic is equally important in the design of NoC application. In this paper, we present an efficient arbitration technique for SoC communications. The presented design has capability to programme the priority of any request dynamically. The design exploits concept of dynamic TDMA to grow and shrink the number of time slot based on active request. The design is based on programmable priority encoder to rotate the priority. The synthesis of proposed arbitration logic has been performed on FPGA vertex 5 device. The maximum operating frequency obtained is 415 MHz. The presented design utilises less hardware resources.
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