Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4 ≤ m ≤ 10) compressors
by Shima Mehrabi; Reza Faghih Mirzaee; Sharareh Zamanzadeh; Keivan Navi; Omid Hashemipour
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 4, No. 4, 2013

Abstract: Compressors play an important role for partial products reduction in the multiplication process. This paper presents a new implementation for the second phase of a 16 × 16-bit multiplier block using wide m:3 compressors such as 8:3, 9:3, and 10:3. Transistor-level and gate-level analysis are conducted to simulate, test, and implement the proposed structures in 90 nm CMOS technology. The proposed structure has 16% higher efficiency compared when only up to 7:3 counters are employed.

Online publication date: Fri, 25-Jul-2014

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