Title: Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4 ≤ m ≤ 10) compressors

Authors: Shima Mehrabi; Reza Faghih Mirzaee; Sharareh Zamanzadeh; Keivan Navi; Omid Hashemipour

Addresses: Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran 1477893855, Iran ' Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran 37541-374, Iran ' Physical Design (CAD) Laboratory, Shahid Beheshti University, G.C., Tehran 1983963113, Iran ' Department of Electrical and Computer Engineering, University of California, Irvine, CA 92697, USA; Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran 1983963113, Iran ' Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran 1983963113, Iran

Abstract: Compressors play an important role for partial products reduction in the multiplication process. This paper presents a new implementation for the second phase of a 16 × 16-bit multiplier block using wide m:3 compressors such as 8:3, 9:3, and 10:3. Transistor-level and gate-level analysis are conducted to simulate, test, and implement the proposed structures in 90 nm CMOS technology. The proposed structure has 16% higher efficiency compared when only up to 7:3 counters are employed.

Keywords: multipliers; compressors; wide counter; partial product reduction; multiplexers; exclusive-OR; XOR; multiplication.

DOI: 10.1504/IJHPSA.2013.058986

International Journal of High Performance Systems Architecture, 2013 Vol.4 No.4, pp.231 - 241

Received: 07 Mar 2013
Accepted: 06 Sep 2013
Published online: 25 Jul 2014 *

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