Network-on-chip architecture design based on mesh-of-tree deterministic routing topology Online publication date: Thu, 04-Dec-2008
by Santanu Kundu, Santanu Chattopadhyay
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 1, No. 3, 2008
Abstract: Network-on-Chip (NoC) is a new paradigm for designing future System-on-Chips (SoCs) where large numbers of Intellectual Property (IP) cores are connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present NoC architecture based on Mesh-of-Tree (MoT) deterministic routing. MoT interconnection has the advantage of having small diameter as well as large bisection width. It is known as the fastest network when considered solely in terms of speed. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented by using FIFO in mixed clock system.
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