Reconfigurable architecture for heterogeneous multi-core and many-core architecture with IoT assistance
by Xuefeng Xing; Jing Cao; Hongtao Zhou; Lei Song; Yanan Qiu
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 10, No. 3/4, 2021

Abstract: This paper discusses a multi-core real-time device reconfigurable and has a sequence of configurations, each lifted to a predetermined state, executing different functions performed by the process. Multiple cores enhance one's efficiency while malfunctioning and under the requirements of powerful applications and programs to run various operations simultaneously with more ease. In this paper, the reconfigurable architecture for heterogeneous multi-core architecture (RA-HMCA) framework is proposed. However, researchers intend to simplify the program by preventing redundancies from being introduced and decrease the risk of threads when satisfying all necessary real-time requirements. The normalisation process is usually used for the removal of redundancies. The suggested solution employs multi-integer linear programming (MILP) technology in the scan stage to have a viable task model. An optically reconfigurable POSIX-based program creates a procedural performance of this technology. A research paper implementation and successful assessment support and validates the findings predicted.

Online publication date: Tue, 22-Feb-2022

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