International Journal of Embedded Systems (6 papers in press)

Regular Issues

• A blockchain-based framework for distributed software testing management in multiprocessor embedded systems  
  by Sabeen Masood, Shoab Ahmad Khan, Ali Hassan 
  Abstract: The collaborative development and testing of complex, multi-processor embedded systems by globally distributed organisations is undermined by a deficit of trust and transparency, as intellectual property (IP) concerns prevent sharing integration-level bug data, leading to isolated, inefficient cycles. This challenge is especially critical for integration bugs, which lack a secure, auditable mechanism for cross-team coordination. This paper introduces a private Hyperledger Fabric v2.4 blockchain with a novel PE-centric governance model that structures smart contracts around hardware interfaces, enabling multi-organisational consensus to validate bugs without exposing proprietary details. Evaluation via an SDR case study with five teams across four organisations shows 3.2 s latency, 120 TPS, and 11 KB per bug. The immutable ledger ensures real-time visibility, reduces rework, and provides verifiable traceability. Consequently, the framework transforms bug management into a secure, collaborative process with superior auditability and IP-aware coordination, reducing integration risk and enhancing reliability in multi-vendor embedded systems.
  Keywords: software testing; embedded systems; blockchain; distributed collaboration; bug management; hardware-software co-design.
  DOI: 10.1504/IJES.2026.10080586
   
  
• Pelican optimisation-driven wrapper method for effective software fault prediction  
  by Himansu Das, Pratiti Mishra, Hrishikesh Kumar, Sanat Kumar Patro, Sushruta Mishra, Mahendra Gourisaria 
  Abstract: Software fault prediction (SFP) plays an important role in the current scenario where software is deeply integrated into day-to-day life. It helps in identifying faulty software before market launch or even before real testing begins. Early identification of software problems reduces both the time and cost required to fix faults. Moreover, feature selection (FS) has emerged as a significant method for selecting the most essential features from a dataset. FS is crucial in the classification process as it minimises the number of attributes through the elimination of noisy and irrelevant subset of features. In this research, a novel wrapper-based FS method using the pelican optimisation algorithm (FSPOA) has been proposed which was combined with four different classifiers: Naive Bayes (NB), K-nearest neighbours (KNN), decision tree (DT) and quadratic discriminant analysis (QDA) and the performance was assessed against several feature selection techniques, including FS using ant colony optimisation (FSACO), genetic algorithm (FSGA), particle swarm optimisation (FSPSO) and differential evolution (FSDE) using 12 open source datasets. The experimental findings showed that, in nearly every test scenario, FSPOA outperformed the existing FS approaches. Additionally, the Friedman and Holm tests were used to statistically confirm the superiority of the proposed FSPOA model.
  Keywords: SFP; FSGA; FSPSO; FSACO; FSDE; FSPOA; wrapper-based FS.
  DOI: 10.1504/IJES.2026.10081109
   
  
• Very large-scale integration floor planning with hybrid meta-heuristic model using walrus-lyrebird optimisation model  
  by Bhavya A. Basavarajappa, Vinay Kumar S. Boregowda 
  Abstract: This paper introduces a walrus exploited lyrebird optimisation model an innovative hybrid meta-heuristic designed specifically for multi-objective VLSI floor planning. The WELO framework combines the exploitation-driven behaviour of walrus-inspired search with the exploration dynamics of lyrebird optimisation, offering a balanced and robust global search mechanism. This hybridisation enables the algorithm to efficiently navigate large, irregular solution spaces while avoiding premature convergence, an issue prevalent in many existing optimisation techniques. The proposed method also incorporates continuous outline constraints and non-slicing floorplan representations, allowing it to handle modern, structurally diverse circuit modules with higher accuracy. Extensive experiments on standard benchmark circuits demonstrate the significant performance impact of WELO. The algorithm achieves notable reductions in chip area, wirelength, and dead space, outperforming state-of-the-art methods across all key metrics. In particular, WELO attains an optimised area utilisation of 0.015 ? 10, highlighting its potential to substantially improve physical design efficiency in advanced VLSI systems.
  Keywords: area; wire length; dead space; VLSI floor plan; WELO algorithm.
  DOI: 10.1504/IJES.2026.10081336
   
  
• Data Shield USB: a secure forensic tool with on-device AI biometric authentication  
  by Osama Hosam, Reem Ismaeil, Humaid Al-Ali 
  Abstract: This paper presents the design, implementation, and evaluation of the Data Shield USB, a forensic tool developed for law enforcement applications. The device integrates multi-factor biometric authentication, military-grade encryption protocols, real-time GPS tracking, and tamper-evident self-wipe mechanisms to ensure the integrity and confidentiality of digital evidence during criminal investigations. Through a systematic methodology encompassing requirement analysis, threat modeling, system design, prototype development, and rigorous testing, we have developed a solution that addresses key challenges in modern digital forensics. Our evaluation results demonstrate strong performance in data extraction speed, encryption efficiency, and resistance to various cyber-physical attacks. The Data Shield USB achieved 99.8% authentication accuracy, data transfer rates exceeding 180 MB/s, and complete resistance to all penetration attempts during security testing. Field trials with law enforcement personnel confirmed the practical utility and reliability of the device in real-world investigative scenarios.
  Keywords: digital forensics; cybersecurity; biometric authentication; encryption; law enforcement technology; evidence integrity; GPS tracking.
  DOI: 10.1504/IJES.2026.10081569
   
  
• Design and analysis of machine learning-based underwater node localisation for wireless sensor networks
  by Ashish Kumar Dass, Sudhir Ranjan Pattanaik, Manjushree Nayak, Bhabani Sankar Gouda 
  Abstract: Accurate three-dimensional (3D) node localisation remains challenging in underwater wireless sensor networks (UWSNs), because the acoustic channel suffers multipath fading, Doppler shifts, variable sound speed and long propagation delays. This paper proposes a hybrid machine-learning framework that couples Kalman-filter denoising with a long short-term memory (LSTM) network and a multilayer artificial neural network (ANN) for 3D position regression, exploiting the temporal structure of sequential ranging data. Across 500 Monte Carlo trials, the scheme achieves a mean localisation error of 1.23 m, a statistically significant (p < 0.001) 50.4% improvement over the strongest of four baselines, and reduces per-cycle energy consumption by 81.4% relative to autonomous underwater vehicle (AUV)-assisted localisation. Computational cost, memory footprint, sound-speed robustness and ablation results indicate a deployable, energy-efficient solution.
  Keywords: underwater wireless sensor networks; UWSNs; wireless sensor networks; node localisation; underwater localisation; three-dimensional localisation; machine learning; Kalman filter; long short-term memory; LSTM; artificial neural networks; ANN; autonomous underwater vehicles; AUV; acoustic channel; sound speed profile; energy consumption; embedded systems.
  
  
• Hardware/software co-design of a low-cost multi-FPGA framework  
  by Ahmed Maache, Lotfi Lehamel, Abdenour Kharouri 
  Abstract: The increasing adoption of field-programmable gate arrays (FPGA) in high-performance and edge computing has intensified the demand for scalable, reconfigurable, and cost-effective multi-FPGA systems. Existing platforms typically rely on specialised interconnects, high-end devices, or domain-specific software, limiting accessibility. This work presents a novel, low-cost, reconfigurable multi-FPGA framework enabling distributed hardware acceleration across commodity DE10-SoC boards. It integrates a custom serial messaging protocol (SMP) over TCP/IP, a multi-user load-balanced architecture, and a runtime-reconfigurable node manager supporting multiple cores per device. Results demonstrate near-linear scalability up to 36 nodes, 8.66 Gbps aggregate throughput, and consistent latency under increasing load. Using a high-level-synthesis (HLS) matrix multiplication kernel, it achieves up to 11.5? speedup over an optimised software baseline. To our knowledge, this is the first framework offering low cost, high-level programmability, dynamic reconfiguration, and multi-user support. It offers a foundation for accessible FPGA computing in research, education, and edge-cloud integration.
  Keywords: multi-FPGA; distributed computing; high-level synthesis; HLS; embedded software/ hardware co-design.
  DOI: 10.1504/IJES.2026.10082326