Design of CMOS full subtractor using 10T for object detection application Online publication date: Mon, 19-Nov-2018
by M. Mahaboob Basha; K. Venkata Ramanaiah; P. Ramana Reddy
International Journal of Reasoning-based Intelligent Systems (IJRIS), Vol. 10, No. 3/4, 2018
Abstract: This paper presents the design of full subtractor (FS), which is able to operate at low voltage and low power. In this method, 2 XOR gates with 1 MUX circuit are used to design the 10T full subtractor in 45nm CMOS technology. In this paper, low cost threshold full subtractor for object detection (LC-TFS-OB) method is presented to utilise the subtractor circuit with minimum number of transistors, which is mostly used in digital circuits and high-speed applications. Voltage sensitive thresholding circuit (VSTC) is introduced in FS to avoid the thresholding problem. From this subtractor, restoring array divider (RAD) is designed for object detection application. Simulation results have shown that with the help of the LC-TFS-OB circuit, area, power, delay and power delay product have minimised in LC-TFS-OB, RAD and object detection application with compared to the conventional methods.
Online publication date: Mon, 19-Nov-2018
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Reasoning-based Intelligent Systems (IJRIS):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email email@example.com