Title: Design of CMOS full subtractor using 10T for object detection application

Authors: M. Mahaboob Basha; K. Venkata Ramanaiah; P. Ramana Reddy

Addresses: Electronics and Communication Engineering Department, S.V.R. Engineering College, India ' Electronics and Communication Engineering, YSR Engineering College, Yogi Vemana University, Proddatur, India ' Electronics and Communication Engineering Department, JNTUA College of Engineering, JNTUCEA, Ananthapuramu, India

Abstract: This paper presents the design of full subtractor (FS), which is able to operate at low voltage and low power. In this method, 2 XOR gates with 1 MUX circuit are used to design the 10T full subtractor in 45nm CMOS technology. In this paper, low cost threshold full subtractor for object detection (LC-TFS-OB) method is presented to utilise the subtractor circuit with minimum number of transistors, which is mostly used in digital circuits and high-speed applications. Voltage sensitive thresholding circuit (VSTC) is introduced in FS to avoid the thresholding problem. From this subtractor, restoring array divider (RAD) is designed for object detection application. Simulation results have shown that with the help of the LC-TFS-OB circuit, area, power, delay and power delay product have minimised in LC-TFS-OB, RAD and object detection application with compared to the conventional methods.

Keywords: full subtractor; voltage sensitive thresholding circuit; VSTC; integer restoring divider; area; power; delay.

DOI: 10.1504/IJRIS.2018.096223

International Journal of Reasoning-based Intelligent Systems, 2018 Vol.10 No.3/4, pp.286 - 295

Received: 27 Jul 2017
Accepted: 13 Oct 2017
Published online: 19 Nov 2018 *

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