FPGA implementation of low complexity super resolution scaling architecture for UHD display systems
by Chidadala Janardhan; K. Venkata Ramanaiah; K. Babulu
International Journal of Engineering Systems Modelling and Simulation (IJESMS), Vol. 16, No. 2, 2025

Abstract: Ultra high definition (UHD) technology has been changing the entertainment industry significantly and its content is severely short of supply due to limited content creators or hard to access due to insufficient network bandwidth. Recent improvements in CMOS image sensor technology, multimedia applications traditional standard display (SD) systems are not sufficient to display high-quality images. Conventional FPGA-based SR methods will exhibit more complexity and requires more hardware resources to perform. This paper describes low complexity super resolution scaling architecture (SRSA) for UHD systems. In our proposed method, bi-cubic interpolation is used for reconstruction the low-frequency image to high-frequency images, these bi-cubic interpolations will have the capability to interpolate 16 nearest neighbours of a pixel. In addition to that high-frequency patches are overlapped to construct super resolutions images with using kernel algorithm. The proposed system generates the output image at 1,600 × 1,600 sizes from 800 × 800 image size. The proposed SRSA super-resolution technique is modelled in Verilog HDL and synthesised in Xilinx Zynq-7000 series FPGA and shown the comparison of area, delay, and power. From the simulation results, the performance of the proposed method can compete over the state of the art methods.

Online publication date: Thu, 06-Mar-2025

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