Performance enhancement of double-gate tunnel FETs using dual-metal and graded-channel configuration
by Chandan Kumar Pandey; Saurabh Chaudhury
International Journal of Nanoparticles (IJNP), Vol. 12, No. 1/2, 2020

Abstract: In this paper, a novel structure of double-gate TFET (DG-TFET) is proposed with graded-channel and dual-metal configuration showing huge reduction in ambipolar conduction. Using TCAD simulations, it is shown that a heavily-doped channel region along with gate metal with lower work-function adjacent to drain region modulates the alignment of band energy at output tunnelling interface in such a manner that an increment in the tunnelling width is occurred. Eventually, a huge reduction in ambipolar conduction is observed in the proposed device. However, performance of the proposed device is shown to be degraded if length of the channel region adjacent to drain is increased beyond a certain value. Through simulations, length-ratio and doping concentration of two channel regions is optimized to achieve the minimum ambipolar current. Additionally, it is demonstrated that ambipolar conduction is completely eliminated in the proposed device even if drain region is doped as heavily as source region.

Online publication date: Tue, 24-Mar-2020

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