Transistor level realisation of power gated FSM Online publication date: Sun, 09-Jul-2017
by Sambhu Nath Pradhan; Priyanka Choudhury; Debanjali Nath
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 9, No. 3, 2017
Abstract: Power can be minimised for the power gated finite state machine (FSM) by suitable partitioning and encoding strategy. Power gating architecture designed previously at FSM level is hypothetical one and may not directly be used for practical implementation of power gated circuit in transistor level. Most of the previous works concern about power reduction of combinational parts only. In this work, a new architecture of power gating design which implements sequential circuit in transistor level has been proposed and considers power consumption of combinational as well as sequential parts. The sequential circuits are obtained after concurrent bi-partitioning and encoding of FSM benchmark circuit. Multi-level realisation of two-level PLA circuit has been done. The architecture is designed such that at a time combinational circuits corresponding to one sub-FSM is power gated by shutting-OFF power supply. Power gating technique in this work shows leakage saving of 47% and total power saving of 53.6%.
Online publication date: Sun, 09-Jul-2017
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