Title: Transistor level realisation of power gated FSM

Authors: Sambhu Nath Pradhan; Priyanka Choudhury; Debanjali Nath

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India ' Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India ' Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India

Abstract: Power can be minimised for the power gated finite state machine (FSM) by suitable partitioning and encoding strategy. Power gating architecture designed previously at FSM level is hypothetical one and may not directly be used for practical implementation of power gated circuit in transistor level. Most of the previous works concern about power reduction of combinational parts only. In this work, a new architecture of power gating design which implements sequential circuit in transistor level has been proposed and considers power consumption of combinational as well as sequential parts. The sequential circuits are obtained after concurrent bi-partitioning and encoding of FSM benchmark circuit. Multi-level realisation of two-level PLA circuit has been done. The architecture is designed such that at a time combinational circuits corresponding to one sub-FSM is power gated by shutting-OFF power supply. Power gating technique in this work shows leakage saving of 47% and total power saving of 53.6%.

Keywords: power gated FSM; finite state machines; low power; multi-level implementation; partitioning-encoding integration; power modelling; programmable logic arrays; PLAs; architecture; simulation; transistors; sequential circuits; energy consumption.

DOI: 10.1504/IJCAET.2017.084903

International Journal of Computer Aided Engineering and Technology, 2017 Vol.9 No.3, pp.351 - 371

Received: 29 Oct 2014
Accepted: 05 Feb 2015

Published online: 27 Mar 2017 *

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