Design of high-performance low-power full adder Online publication date: Fri, 18-Apr-2014
by K. Nehru; A. Shanmugam
International Journal of Computer Applications in Technology (IJCAT), Vol. 49, No. 2, 2014
Abstract: Full adder is an essential component for the design and development of all types of processor. This project introduces the design of high-performance low-power full adder which acquires least area with the lowest transistor count. The high-performance low-power full adder is designed and the implementation of a 32-bit ripple carry adder based on high-performance low-power full adder circuit is described, and comparison is made with other previously designed full adders. The high-performance low-power full adder circuit is designed and the simulation has been carried out on Tanner EDA tool. The result shows that the proposed high-performance low-power full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and considerably increases the speed.
Online publication date: Fri, 18-Apr-2014
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