Title: Design of high-performance low-power full adder

Authors: K. Nehru; A. Shanmugam

Addresses: Department of Electronics and Communication Engineering, R.M.D Engineering College, Chennai 601206, India ' Department of Electronics and Communication Engineering, R.M.D Engineering College, Chennai 601206, India

Abstract: Full adder is an essential component for the design and development of all types of processor. This project introduces the design of high-performance low-power full adder which acquires least area with the lowest transistor count. The high-performance low-power full adder is designed and the implementation of a 32-bit ripple carry adder based on high-performance low-power full adder circuit is described, and comparison is made with other previously designed full adders. The high-performance low-power full adder circuit is designed and the simulation has been carried out on Tanner EDA tool. The result shows that the proposed high-performance low-power full adder is an efficient full adder cell with least MOS transistor count that reduces the high power consumption and considerably increases the speed.

Keywords: low power; full adders; VLSI design; very large scale integration; XOR gate; MOS transistor count; ripple carry adder; simulation.

DOI: 10.1504/IJCAT.2014.060524

International Journal of Computer Applications in Technology, 2014 Vol.49 No.2, pp.134 - 140

Available online: 18 Apr 2014 *

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