Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processing Online publication date: Tue, 23-Jul-2013
by Amir Gargouri; Mohamed Krid; Dorra Sellami Masmoudi
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 4, No. 3, 2013
Abstract: A key task in the hardware implementation of neural networks is the design of activation functions. We focus in this paper on hardware driven simple implementation of a bell-shaped function (BSF) avoiding complexity and reducing hardware resources with efficient on-chip learning. This implementation is done in pulse mode to take advantage of its valuable features, significantly reducing the hardware cost. The proposed design is flexible and scalable enabling several image processing potential tasks. A first application is devoted to image denoising where a comparison with some existing denoising techniques demonstrates the efficiency of the proposed approach. As a second application, we consider edge detection operation and good approximation features are accordingly obtained. The corresponding design is implemented on a Virtex-II-PRO FPGA platform. Synthesis results prove that the bell-shaped PMNN is not cumbersome, and provides higher performances versus other PMNN architectures in terms of computing speed and required hardware resources.
Online publication date: Tue, 23-Jul-2013
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