Automated transistor width optimisation algorithms for digital circuits Online publication date: Sat, 19-Jul-2014
by Satish Chandra Tiwari; Kunwar Singh; Maneesha Gupta
International Journal of Embedded Systems (IJES), Vol. 5, No. 1/2, 2013
Abstract: This paper presents two novel automated transistor width optimisation algorithms based on Levenberg-Marquardt (LM) algorithm (embedded in SPICE) and logical effort theory proposed by Sutherland et al. (2004). This paper has incorporated the complete logical effort theory from scratch in TCL; hence, it works independent of SPICE tool and can optimise any number of transistors present in circuit. The algorithm can be used as open source optimisation tool and modifications can be done to it according to the need. The proposed algorithms can be utilised for automated library cell characterisation where precise and large numbers of driving strength cells are required. Since the algorithms are automation based, they can play a pivotal role in development of library less synthesis. Optimisations results using proposed algorithms were obtained for both sequential logic blocks (flip-flop) and combinational logic blocks (basic logic gates). Both the algorithms have their own advantages and disadvantages.
Online publication date: Sat, 19-Jul-2014
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Embedded Systems (IJES):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email firstname.lastname@example.org