Title: Automated transistor width optimisation algorithms for digital circuits

Authors: Satish Chandra Tiwari; Kunwar Singh; Maneesha Gupta

Addresses: Department of ECE, NSIT, Room No. 15, Block-IV, Dwarka, New Delhi, 110078, India ' Department of Electrical Engineering, Delhi Technological University, Room No. FW11-SF1, D.T.U., Delhi, 110042, India ' Department of ECE, NSIT, Room No. 18, Block-IV, Dwarka, New Delhi, 110078, India

Abstract: This paper presents two novel automated transistor width optimisation algorithms based on Levenberg-Marquardt (LM) algorithm (embedded in SPICE) and logical effort theory proposed by Sutherland et al. (2004). This paper has incorporated the complete logical effort theory from scratch in TCL; hence, it works independent of SPICE tool and can optimise any number of transistors present in circuit. The algorithm can be used as open source optimisation tool and modifications can be done to it according to the need. The proposed algorithms can be utilised for automated library cell characterisation where precise and large numbers of driving strength cells are required. Since the algorithms are automation based, they can play a pivotal role in development of library less synthesis. Optimisations results using proposed algorithms were obtained for both sequential logic blocks (flip-flop) and combinational logic blocks (basic logic gates). Both the algorithms have their own advantages and disadvantages.

Keywords: network on chip; NOC; flip-flops; automated optimisation; logical effort; Levenberg-Marquardt algorithms; SPICE; VLSI; transistor width optimisation; digital circuits.

DOI: 10.1504/IJES.2013.052172

International Journal of Embedded Systems, 2013 Vol.5 No.1/2, pp.44 - 52

Received: 01 Mar 2012
Accepted: 11 Sep 2012

Published online: 15 Feb 2013 *

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