A RISC architecture for 2DLNS-based signal processing Online publication date: Sat, 21-Mar-2015
by M. Azarmehr, R. Muscedere
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 3, No. 2/3, 2011
Abstract: The multi-dimensional logarithmic number system (MDLNS) provides a reduction in the size of the number representation and promises a lower cost realisation of arithmetic operations. The non-linear nature of the representation and independency of the parallel-based computations combined with multi-digit extensions of the MDLNS representations along with simplified arithmetic operations, make MDLNS suitable for some multiplication intensive DSP applications. The work presented in this paper is the design and implementation of a 2DLNS-based processor architecture. This CPU takes advantage of a relatively simple architecture and a well designed organisation which greatly improves the implementation of many DSP algorithms. An assembly programme is also written to implement a 2DLNS-based filterbank architecture. This implementation demonstrates the efficiency and ease of use of 2DLNS CPU in real applications.
Online publication date: Sat, 21-Mar-2015
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of High Performance Systems Architecture (IJHPSA):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email firstname.lastname@example.org