Title: A RISC architecture for 2DLNS-based signal processing

Authors: M. Azarmehr, R. Muscedere

Addresses: Department of Electrical and Computer Engineering, University of Windsor, 401 Sunset Avenue, Windsor, Ontario, Canada. ' Department of Electrical and Computer Engineering, University of Windsor, 401 Sunset Avenue, Windsor, Ontario, Canada

Abstract: The multi-dimensional logarithmic number system (MDLNS) provides a reduction in the size of the number representation and promises a lower cost realisation of arithmetic operations. The non-linear nature of the representation and independency of the parallel-based computations combined with multi-digit extensions of the MDLNS representations along with simplified arithmetic operations, make MDLNS suitable for some multiplication intensive DSP applications. The work presented in this paper is the design and implementation of a 2DLNS-based processor architecture. This CPU takes advantage of a relatively simple architecture and a well designed organisation which greatly improves the implementation of many DSP algorithms. An assembly programme is also written to implement a 2DLNS-based filterbank architecture. This implementation demonstrates the efficiency and ease of use of 2DLNS CPU in real applications.

Keywords: MDLNS representation; processors; reduced instruction set computer; RISC architecture; CPU; multiplication; FIR filter; multiply and accumulation; MAC; filterbank architecture; digital signal processing; DSP.

DOI: 10.1504/IJHPSA.2011.040467

International Journal of High Performance Systems Architecture, 2011 Vol.3 No.2/3, pp.149 - 156

Received: 12 Dec 2009
Accepted: 01 Jul 2010
Published online: 21 Mar 2015 *

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