A functional model of silicon carbide JFET and its use in the analysis of switching-transient and impact of gate resistor, miller effect and parasitic inductance Online publication date: Mon, 25-Jan-2010
by Hua Bai, Sanbo Pan, Chris Mi, Tim Lin
International Journal of Power Electronics (IJPELEC), Vol. 2, No. 2, 2010
Abstract: A functional model of silicon carbide (SiC) JFET was developed to study its performance. Based on this model, the gate resistor in the gate drive circuit of SiC JFET is optimised with comprehensive consideration of gate current impact, miller effect, switching speed and voltage spikes. The switch on oscillation caused by parasitic inductance is analysed and methods are proposed to mitigate the oscillation. Experiments on a 300 V prototype validated the proposed model.
Online publication date: Mon, 25-Jan-2010
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