On-chip implementation of multiprocessor networks and switch fabrics Online publication date: Sat, 03-Jan-2009
by Terry Tao Ye, Giovanni De Micheli
International Journal of Embedded Systems (IJES), Vol. 3, No. 4, 2008
Abstract: On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon foorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular. Therefore, traditional ASIC floorplanning methodologies that perform macro placement are not suitable for MPSoC designs. We propose an automated MPSoC physical planning methodology. REGULAY can generate an optimal floorplan for different topologies under different design constraints. Compared with traditional floorplanning approaches, REGULAY shows significant advantages in reducing the total interconnect wirelength while preserving the regularity and hierarchy of the network topology.
Online publication date: Sat, 03-Jan-2009
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