Authors: Terry Tao Ye, Giovanni De Micheli
Addresses: R/D Center for Logistics and Supply Chain Management (LSCM), Hong Kong. ' EPFL, Switzerland
Abstract: On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon foorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular. Therefore, traditional ASIC floorplanning methodologies that perform macro placement are not suitable for MPSoC designs. We propose an automated MPSoC physical planning methodology. REGULAY can generate an optimal floorplan for different topologies under different design constraints. Compared with traditional floorplanning approaches, REGULAY shows significant advantages in reducing the total interconnect wirelength while preserving the regularity and hierarchy of the network topology.
Keywords: NoCs; network on chips; MPSoCs; structures interconnect; network interface; multiprocessor networks; switch fabrics; router; link; physical design; silicon foorplan; network topology.
International Journal of Embedded Systems, 2008 Vol.3 No.4, pp.209 - 218
Available online: 03 Jan 2009 *Full-text access for editors Access for subscribers Purchase this article Comment on this article