Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips Online publication date: Sun, 14-Sep-2008
by Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr
International Journal of Embedded Systems (IJES), Vol. 3, No. 3, 2008
Abstract: In this paper, a SystemC based system level design methodology is proposed, which enables the designer to reason about the architecture on a much higher level of abstraction. The goal of this methodology is to define a system architecture, which provides sufficient performance, flexibility and cost efficiency as required by demanding applications, such as broadband networking or wireless communications. Co-simulating multiple levels of abstraction simultaneously enables reuse of abstract models of the functional verification of synthesisable implementation models. We share our experiences with special emphasis on the architecture exploration phase, where several architectural alternatives are evaluated with respect to their impact on the system performance.
Online publication date: Sun, 14-Sep-2008
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