Title: Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips
Authors: Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr
Addresses: Co Ware, Inc., USA. ' Co Ware, Inc., Japan. ' Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany. ' Co Ware, Inc., USA. ' Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany. ' Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany
Abstract: In this paper, a SystemC based system level design methodology is proposed, which enables the designer to reason about the architecture on a much higher level of abstraction. The goal of this methodology is to define a system architecture, which provides sufficient performance, flexibility and cost efficiency as required by demanding applications, such as broadband networking or wireless communications. Co-simulating multiple levels of abstraction simultaneously enables reuse of abstract models of the functional verification of synthesisable implementation models. We share our experiences with special emphasis on the architecture exploration phase, where several architectural alternatives are evaluated with respect to their impact on the system performance.
Keywords: transaction level modelling; SystemC; simulation; virtual architecture mapping; system-on-chip; SoC; system architecture.
International Journal of Embedded Systems, 2008 Vol.3 No.3, pp.150 - 159
Published online: 14 Sep 2008 *Full-text access for editors Access for subscribers Purchase this article Comment on this article