Low power transistor level synthesis of finite state machines using a novel dual gating technique
by Abhishek Nag; Subhajit Das; Sambhu Nath Pradhan
International Journal of Embedded Systems (IJES), Vol. 13, No. 4, 2020

Abstract: In this work, an efficient technique of clock and power gating is concurrently introduced in finite state machines (FSM) with a view to minimising the overall power dissipation. The proposed power gating concept works on the principle of shutting down the power supply to the FSM during periods of inactivity. The extraction of the inactivity criteria is based on the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating, on the other hand, disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The idea of implementing the gating in both the state logic as well as output logic is introduced in this work. The proposed approach has been introduced in three benchmark FSM circuits, simulated and synthesised in Cadence digital design tool. The results indicate a maximum of 73% total power savings (dynamic and static) with an average penalty of 27% area (approx.).

Online publication date: Tue, 27-Oct-2020

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Embedded Systems (IJES):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com