Title: Low power transistor level synthesis of finite state machines using a novel dual gating technique

Authors: Abhishek Nag; Subhajit Das; Sambhu Nath Pradhan

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799046, India ' Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799046, India ' Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799046, India

Abstract: In this work, an efficient technique of clock and power gating is concurrently introduced in finite state machines (FSM) with a view to minimising the overall power dissipation. The proposed power gating concept works on the principle of shutting down the power supply to the FSM during periods of inactivity. The extraction of the inactivity criteria is based on the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating, on the other hand, disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The idea of implementing the gating in both the state logic as well as output logic is introduced in this work. The proposed approach has been introduced in three benchmark FSM circuits, simulated and synthesised in Cadence digital design tool. The results indicate a maximum of 73% total power savings (dynamic and static) with an average penalty of 27% area (approx.).

Keywords: clock gating; power gating; finite state machine; FSM; self-loops.

DOI: 10.1504/IJES.2020.110657

International Journal of Embedded Systems, 2020 Vol.13 No.4, pp.431 - 438

Accepted: 08 Sep 2019
Published online: 10 Aug 2020 *

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